-- 
-- psg_ay_3_8910.vhd
--   Programmable Sound Generator (AY-3-8910)
--   Revision 1.00
-- 
-- Copyright (c) 2008 Takayuki Hara
-- All rights reserved.
-- 
-- Redistribution and use of this source code or any derivative works, are 
-- permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, 
--    this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright 
--    notice, this list of conditions and the following disclaimer in the 
--    documentation and/or other materials provided with the distribution.
-- 3. Redistributions may not be sold, nor may they be used in a commercial 
--    product or activity without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 
-- CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 

--------------------------------------------------------------------
LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PSG_AY_3_8910_TONE_GENERATOR IS
	PORT(
		CLK			: IN	STD_LOGIC;
		RESET		: IN	STD_LOGIC;
		ACT			: IN	STD_LOGIC;
		TONE_OUT	: OUT	STD_LOGIC;
		REG_TP		: IN	STD_LOGIC_VECTOR( 11 DOWNTO 0 )
	);
END PSG_AY_3_8910_TONE_GENERATOR;

ARCHITECTURE RTL OF PSG_AY_3_8910_TONE_GENERATOR IS
	SIGNAL FF_TP_CNT	: STD_LOGIC_VECTOR( 11 DOWNTO 0 );
	SIGNAL FF_TONE_OUT	: STD_LOGIC;
	SIGNAL W_CNT_END	: STD_LOGIC;
BEGIN

	TONE_OUT	<= FF_TONE_OUT;
	W_CNT_END	<= '1' WHEN( FF_TP_CNT = "000000000000" )ELSE '0';

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_TP_CNT <= (OTHERS => '1');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( W_CNT_END = '1' )THEN
					FF_TP_CNT <= REG_TP;
				ELSE
					FF_TP_CNT <= FF_TP_CNT - 1;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_TONE_OUT <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( W_CNT_END = '1' )THEN
					FF_TONE_OUT <= NOT FF_TONE_OUT;
				ELSE
					-- HOLD
				END IF;
			END IF;
		END IF;
	END PROCESS;
END RTL;

--------------------------------------------------------------------
LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PSG_AY_3_8910_NOISE_GENERATOR IS
	PORT(
		CLK			: IN	STD_LOGIC;
		RESET		: IN	STD_LOGIC;
		ACT			: IN	STD_LOGIC;
		NOISE_OUT	: OUT	STD_LOGIC;
		REG_NP		: IN	STD_LOGIC_VECTOR(  4 DOWNTO 0 )
	);
END PSG_AY_3_8910_NOISE_GENERATOR;

ARCHITECTURE RTL OF PSG_AY_3_8910_NOISE_GENERATOR IS
	SIGNAL FF_NP_CNT	: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL FF_RAND		: STD_LOGIC_VECTOR( 16 DOWNTO 0 );
	SIGNAL W_CNT_END	: STD_LOGIC;
BEGIN

	NOISE_OUT	<= FF_RAND(0);
	W_CNT_END	<= '1' WHEN( FF_NP_CNT = "00000" )ELSE '0';

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_NP_CNT <= (OTHERS => '1');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( W_CNT_END = '1' )THEN
					FF_NP_CNT <= REG_NP;
				ELSE
					FF_NP_CNT <= FF_NP_CNT - 1;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_RAND <= "00000000000000001";
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( W_CNT_END = '1' )THEN
					FF_RAND <= (FF_RAND(0) XOR FF_RAND(3)) & FF_RAND( 16 DOWNTO 1 );
				ELSE
					-- HOLD
				END IF;
			END IF;
		END IF;
	END PROCESS;
END RTL;

--------------------------------------------------------------------
LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PSG_AY_3_8910_ENVELOPE_GENERATOR IS
	PORT(
		CLK			: IN	STD_LOGIC;
		RESET		: IN	STD_LOGIC;
		ACT			: IN	STD_LOGIC;
		START		: IN	STD_LOGIC;
		ENV_OUT		: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_EP		: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
		REG_ENV		: IN	STD_LOGIC_VECTOR(  3 DOWNTO 0 )
	);
END PSG_AY_3_8910_ENVELOPE_GENERATOR;

ARCHITECTURE RTL OF PSG_AY_3_8910_ENVELOPE_GENERATOR IS
	SIGNAL FF_EP_CNT	: STD_LOGIC_VECTOR( 15 DOWNTO 0 );
	SIGNAL FF_ENV_INV	: STD_LOGIC;
	SIGNAL FF_ENV		: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_ENV_HOLD	: STD_LOGIC;
	SIGNAL W_CNT_END	: STD_LOGIC;
	SIGNAL W_ENV_ZERO	: STD_LOGIC;
	SIGNAL W_HOLD		: STD_LOGIC;
	SIGNAL W_INV_INV	: STD_LOGIC;
BEGIN

	ENV_OUT		<= NOT FF_ENV WHEN( FF_ENV_INV = '1' )ELSE FF_ENV;

	W_CNT_END	<= '1' WHEN( FF_EP_CNT = "0000000000000000" )ELSE '0';

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_EP_CNT <= (OTHERS => '1');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( W_CNT_END = '1' OR START = '1' )THEN
					FF_EP_CNT <= REG_EP;
				ELSE
					FF_EP_CNT <= FF_EP_CNT - 1;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	W_HOLD		<= (NOT REG_ENV(3)) OR REG_ENV(0);
	W_INV_INV	<= (REG_ENV(2) AND (NOT REG_ENV(3))) OR (REG_ENV(1) AND REG_ENV(3));
	W_ENV_ZERO	<= '1' WHEN( FF_ENV = "0000" )ELSE '0';

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_ENV <= "0000";
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( START = '1' )THEN
					FF_ENV <= "1111";
				ELSIF( W_CNT_END = '1' )THEN
					IF( W_ENV_ZERO = '1' )THEN
						IF( W_HOLD = '1' )THEN
							-- HOLD
						ELSE
							FF_ENV <= "1111";
						END IF;
					ELSE
						FF_ENV <= FF_ENV - 1;
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_ENV_HOLD <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( START = '1' )THEN
					FF_ENV_HOLD <= '0';
				ELSIF( (W_CNT_END AND W_ENV_ZERO) = '1' )THEN
					FF_ENV_HOLD <= W_HOLD;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_ENV_INV <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ACT = '1' )THEN
				IF( START = '1' )THEN
					FF_ENV_INV <= REG_ENV(2);
				ELSIF( W_CNT_END = '1' )THEN
					IF( (W_ENV_ZERO AND W_INV_INV AND (NOT FF_ENV_HOLD)) = '1' )THEN
						FF_ENV_INV <= NOT FF_ENV_INV;
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END RTL;

--------------------------------------------------------------------
LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY PSG_AY_3_8910 IS
	PORT(
		CLK			: IN	STD_LOGIC;								-- base clock
		RESET		: IN	STD_LOGIC;
		CLKENA		: IN	STD_LOGIC;								-- 3.58MHz timing pulse
		REQ			: IN	STD_LOGIC;
		ACK			: OUT	STD_LOGIC;
		WRT			: IN	STD_LOGIC;
		ADR			: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
		DAO			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		DAI			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		WAVE		: OUT	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
		PAI			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		PBI			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		PAO			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		PBO			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 )
	);
END PSG_AY_3_8910;

ARCHITECTURE RTL OF PSG_AY_3_8910 IS

	COMPONENT PSG_AY_3_8910_TONE_GENERATOR
		PORT(
			CLK			: IN	STD_LOGIC;
			RESET		: IN	STD_LOGIC;
			ACT			: IN	STD_LOGIC;
			TONE_OUT	: OUT	STD_LOGIC;
			REG_TP		: IN	STD_LOGIC_VECTOR( 11 DOWNTO 0 )
		);
	END COMPONENT;

	COMPONENT PSG_AY_3_8910_NOISE_GENERATOR
		PORT(
			CLK			: IN	STD_LOGIC;
			RESET		: IN	STD_LOGIC;
			ACT			: IN	STD_LOGIC;
			NOISE_OUT	: OUT	STD_LOGIC;
			REG_NP		: IN	STD_LOGIC_VECTOR(  4 DOWNTO 0 )
		);
	END COMPONENT;

	COMPONENT PSG_AY_3_8910_ENVELOPE_GENERATOR
		PORT(
			CLK			: IN	STD_LOGIC;
			RESET		: IN	STD_LOGIC;
			ACT			: IN	STD_LOGIC;
			START		: IN	STD_LOGIC;
			ENV_OUT		: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_EP		: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
			REG_ENV		: IN	STD_LOGIC_VECTOR(  3 DOWNTO 0 )
		);
	END COMPONENT;

	SIGNAL REG_PTR			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_TP_A			: STD_LOGIC_VECTOR( 11 DOWNTO 0 );
	SIGNAL REG_TP_B			: STD_LOGIC_VECTOR( 11 DOWNTO 0 );
	SIGNAL REG_TP_C			: STD_LOGIC_VECTOR( 11 DOWNTO 0 );
	SIGNAL REG_NP			: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL REG_DISABLE		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL REG_VOL_A		: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL REG_VOL_B		: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL REG_VOL_C		: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL REG_EP			: STD_LOGIC_VECTOR( 15 DOWNTO 0 );
	SIGNAL REG_ENV			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_PIO_A		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL REG_PIO_B		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL FF_DIVCLK		: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL FF_ENV_START		: STD_LOGIC;
	SIGNAL FF_OUT_VOL		: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_WAVE			: STD_LOGIC_VECTOR(  9 DOWNTO 0 );

	SIGNAL W_ACT			: STD_LOGIC;
	SIGNAL W_ACT2			: STD_LOGIC;
	SIGNAL W_REG_READ		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL W_OUT_A			: STD_LOGIC;
	SIGNAL W_OUT_B			: STD_LOGIC;
	SIGNAL W_OUT_C			: STD_LOGIC;
	SIGNAL W_OUT			: STD_LOGIC;
	SIGNAL W_VOL			: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL W_LINEAR_VOL		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL TONE_A			: STD_LOGIC;
	SIGNAL TONE_B			: STD_LOGIC;
	SIGNAL TONE_C			: STD_LOGIC;
	SIGNAL NOISE			: STD_LOGIC;
	SIGNAL ENVELOPE_OUT		: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
BEGIN

	ACK <= REQ;

	----------------------------------------------------------------
	-- CLOCK DIVIDER
	----------------------------------------------------------------
	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_DIVCLK <= (OTHERS => '0');
		ELSIF (CLK'EVENT AND CLK = '1') THEN
			IF( CLKENA = '1' )THEN
				FF_DIVCLK <= FF_DIVCLK - 1;
			END IF;
		END IF;
	END PROCESS;

	W_ACT  <= '1' WHEN( FF_DIVCLK( 3 DOWNTO 0 ) = "0000"  AND CLKENA = '1' )ELSE '0';
	W_ACT2 <= '1' WHEN( FF_DIVCLK               = "00000" AND CLKENA = '1' )ELSE '0';

	----------------------------------------------------------------
	-- REGISTER READ
	----------------------------------------------------------------
	WITH REG_PTR SELECT W_REG_READ <=
		(			REG_TP_A(  7 DOWNTO 0 ))	WHEN "0000",
		("0000"	&	REG_TP_A( 11 DOWNTO 8 ))	WHEN "0001",
		(			REG_TP_B(  7 DOWNTO 0 ))	WHEN "0010",
		("0000"	&	REG_TP_B( 11 DOWNTO 8 ))	WHEN "0011",
		(			REG_TP_C(  7 DOWNTO 0 ))	WHEN "0100",
		("0000"	&	REG_TP_C( 11 DOWNTO 8 ))	WHEN "0101",
		("000"	&	REG_NP				   )	WHEN "0110",
		(REG_DISABLE					   )	WHEN "0111",
		("000"	&	REG_VOL_A			   )	WHEN "1000",
		("000"	&	REG_VOL_B			   )	WHEN "1001",
		("000"	&	REG_VOL_C			   )	WHEN "1010",
		(REG_EP(  7 DOWNTO 0 )			   )	WHEN "1011",
		(REG_EP( 15 DOWNTO 8 )			   )	WHEN "1100",
		("0000"	& REG_ENV				   )	WHEN "1101",
		(REG_PIO_A						   )	WHEN "1110",
		(REG_PIO_B						   )	WHEN "1111",
		(OTHERS => 'X')							WHEN OTHERS;

	DAO <= W_REG_READ WHEN( ADR = "10" )ELSE (OTHERS => '1');

	----------------------------------------------------------------
	-- REGISTER WRITE
	----------------------------------------------------------------
	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			REG_PTR	<= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( REQ = '1' AND WRT = '1' AND ADR = "00" )THEN
				-- REGISTER POINTER
				REG_PTR	<= DAI( 3 DOWNTO 0 );
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			REG_TP_A	<= (OTHERS => '1');
			REG_TP_B	<= (OTHERS => '1');
			REG_TP_C	<= (OTHERS => '1');
			REG_NP		<= (OTHERS => '1');
			REG_DISABLE	<= (OTHERS => '1');
			REG_VOL_A	<= (OTHERS => '1');
			REG_VOL_B	<= (OTHERS => '1');
			REG_VOL_C	<= (OTHERS => '1');
			REG_EP		<= (OTHERS => '1');
			REG_ENV		<= (OTHERS => '1');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( REQ = '1' AND WRT = '1' AND ADR = "01" )THEN
				-- PSG REGISTERS
				CASE REG_PTR IS
				WHEN "0000" => REG_TP_A(  7 DOWNTO 0 )	<= DAI;
				WHEN "0001" => REG_TP_A( 11 DOWNTO 8 )	<= DAI( 3 DOWNTO 0 );
				WHEN "0010" => REG_TP_B(  7 DOWNTO 0 )	<= DAI;
				WHEN "0011" => REG_TP_B( 11 DOWNTO 8 )	<= DAI( 3 DOWNTO 0 );
				WHEN "0100" => REG_TP_C(  7 DOWNTO 0 )	<= DAI;
				WHEN "0101" => REG_TP_C( 11 DOWNTO 8 )	<= DAI( 3 DOWNTO 0 );
				WHEN "0110" => REG_NP					<= DAI( 4 DOWNTO 0 );
				WHEN "0111" => REG_DISABLE				<= DAI( 7 DOWNTO 0 );
				WHEN "1000" => REG_VOL_A				<= DAI( 4 DOWNTO 0 );
				WHEN "1001" => REG_VOL_B				<= DAI( 4 DOWNTO 0 );
				WHEN "1010" => REG_VOL_C				<= DAI( 4 DOWNTO 0 );
				WHEN "1011" => REG_EP(  7 DOWNTO 0 )	<= DAI;
				WHEN "1100" => REG_EP( 15 DOWNTO 8 )	<= DAI;
				WHEN "1101" => REG_ENV					<= DAI(  3 DOWNTO 0 );
				WHEN OTHERS => NULL;
				END CASE;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			REG_PIO_A <= (OTHERS => '1');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( REG_DISABLE(6) = '0' )THEN
				REG_PIO_A <= PAI;
			ELSIF( REQ = '1' AND WRT = '1' AND ADR = "01" AND REG_PTR = "1110" )THEN
				REG_PIO_A <= DAI;
			END IF;
		END IF;
	END PROCESS;

	PAO <= REG_PIO_A;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			REG_PIO_B <= (OTHERS => '1');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( REG_DISABLE(7) = '0' )THEN
				REG_PIO_B <= PBI;
			ELSIF( REQ = '1' AND WRT = '1' AND ADR = "01" AND REG_PTR = "1111" )THEN
				REG_PIO_B <= DAI;
			END IF;
		END IF;
	END PROCESS;

	PBO <= REG_PIO_B;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_ENV_START <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( REQ = '1' AND WRT = '1' AND ADR = "01" AND REG_PTR = "1101" )THEN
				FF_ENV_START <= '1';
			ELSIF( W_ACT2 = '1' )THEN
				FF_ENV_START <= '0';
			END IF;
		END IF;
	END PROCESS;

	----------------------------------------------------------------
	-- TONE GENERATOR
	----------------------------------------------------------------
	U_TONE_A: PSG_AY_3_8910_TONE_GENERATOR
	PORT MAP (
		CLK			=> CLK				,
		RESET		=> RESET			,
		ACT			=> W_ACT			,
		TONE_OUT	=> TONE_A			,
		REG_TP		=> REG_TP_A			
	);

	U_TONE_B: PSG_AY_3_8910_TONE_GENERATOR
	PORT MAP (
		CLK			=> CLK				,
		RESET		=> RESET			,
		ACT			=> W_ACT			,
		TONE_OUT	=> TONE_B			,
		REG_TP		=> REG_TP_B			
	);

	U_TONE_C: PSG_AY_3_8910_TONE_GENERATOR
	PORT MAP (
		CLK			=> CLK				,
		RESET		=> RESET			,
		ACT			=> W_ACT			,
		TONE_OUT	=> TONE_C			,
		REG_TP		=> REG_TP_C			
	);

	----------------------------------------------------------------
	-- NOISE GENERATOR 
	----------------------------------------------------------------
	U_NOISE: PSG_AY_3_8910_NOISE_GENERATOR
	PORT MAP (
		CLK			=> CLK				,
		RESET		=> RESET			,
		ACT			=> W_ACT			,
		NOISE_OUT	=> NOISE			,
		REG_NP		=> REG_NP			
	);

	----------------------------------------------------------------
	-- ENVELOPE GENERATOR
	----------------------------------------------------------------
	U_ENVELOPE: PSG_AY_3_8910_ENVELOPE_GENERATOR
	PORT MAP (
		CLK			=> CLK				,
		RESET		=> RESET			,
		ACT			=> W_ACT2			,
		START		=> FF_ENV_START		,
		ENV_OUT		=> ENVELOPE_OUT		,
		REG_EP		=> REG_EP			,
		REG_ENV		=> REG_ENV			
	);

	----------------------------------------------------------------
	-- ENABLER
	----------------------------------------------------------------
	W_OUT_A <= (TONE_A OR REG_DISABLE(0)) AND (NOISE OR REG_DISABLE(3));
	W_OUT_B <= (TONE_B OR REG_DISABLE(1)) AND (NOISE OR REG_DISABLE(4));
	W_OUT_C <= (TONE_C OR REG_DISABLE(2)) AND (NOISE OR REG_DISABLE(5));

	WITH FF_DIVCLK( 1 DOWNTO 0 )SELECT W_OUT <=
		W_OUT_A				WHEN "00",
		W_OUT_B				WHEN "01",
		W_OUT_C				WHEN "10",
		'0'					WHEN OTHERS;

	WITH FF_DIVCLK( 1 DOWNTO 0 )SELECT W_VOL <=
		REG_VOL_A			WHEN "00",
		REG_VOL_B			WHEN "01",
		REG_VOL_C			WHEN "10",
		"00000"				WHEN OTHERS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_OUT_VOL <= "0000";
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( CLKENA = '1' )THEN
				IF( W_OUT = '0' )THEN
					FF_OUT_VOL <= "0000";
				ELSIF( W_VOL(4) = '1' )THEN
					FF_OUT_VOL <= ENVELOPE_OUT;
				ELSE
					FF_OUT_VOL <= W_VOL( 3 DOWNTO 0 );
				END IF;
			END IF;
		END IF;
	END PROCESS;

	WITH FF_OUT_VOL SELECT W_LINEAR_VOL <=
		"11111111" WHEN "1111",
		"10110100" WHEN "1110",
		"01111111" WHEN "1101",
		"01011010" WHEN "1100",
		"00111111" WHEN "1011",
		"00101101" WHEN "1010",
		"00011111" WHEN "1001",
		"00010110" WHEN "1000",
		"00001111" WHEN "0111",
		"00001011" WHEN "0110",
		"00000111" WHEN "0101",
		"00000101" WHEN "0100",
		"00000011" WHEN "0011",
		"00000010" WHEN "0010",
		"00000001" WHEN "0001",
		"00000000" WHEN "0000",
		"XXXXXXXX" WHEN OTHERS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			FF_WAVE <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( CLKENA = '1' )THEN
				IF( FF_DIVCLK( 1 DOWNTO 0 ) = "00" )THEN
					FF_WAVE <= (OTHERS => '0');
				ELSE
					FF_WAVE <= FF_WAVE + ("00" & W_LINEAR_VOL);
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET, CLK )
	BEGIN
		IF( RESET = '1' )THEN
			WAVE <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( CLKENA = '1' )THEN
				IF( FF_DIVCLK( 1 DOWNTO 0 ) = "00" )THEN
					WAVE <= FF_WAVE;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END RTL;