-------------------------------------------------------------------------------
--  th9958.vhd
--  VDP V9958 compatible IP
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TH9958 IS
	PORT(
		CLK					: IN	STD_LOGIC;
		RESET_N				: IN	STD_LOGIC;
		ENABLE				: IN	STD_LOGIC;
		-- CPU INTERFACE
		REQ					: IN	STD_LOGIC;
		ACK					: OUT	STD_LOGIC;
		WRT					: IN	STD_LOGIC;
		ADR					: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
		DBO					: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		DBI					: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		-- INTERRUPT REQUEST
		INTR_N				: OUT	STD_LOGIC;
		-- DRAM INTERFACE
		DRAM_OE_N			: OUT	STD_LOGIC;
		DRAM_WE_N			: OUT	STD_LOGIC;
		DRAM_A				: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
		DRAM_Q				: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
		DRAM_D				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		-- VIDEO OUTPUT
		VIDEO_R				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		VIDEO_G				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		VIDEO_B				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		VIDEO_HS_N			: OUT	STD_LOGIC;
		VIDEO_VS_N			: OUT	STD_LOGIC;
		VIDEO_CS_N			: OUT	STD_LOGIC;
		VIDEO_DH_CLK		: OUT	STD_LOGIC;
		VIDEO_DL_CLK		: OUT	STD_LOGIC;
		-- OPTION MODE
		HS_MODE				: IN	STD_LOGIC;
		VGA_MODE			: IN	STD_LOGIC
	);
END TH9958;

ARCHITECTURE RTL OF TH9958 IS

	COMPONENT TH9958_REGISTER
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;
			-- CPU I/F
			ADR					: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
			REQ					: IN	STD_LOGIC;
			ACK					: OUT	STD_LOGIC;
			WRT					: IN	STD_LOGIC;
			DBI					: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			DBO					: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			-- DRAM I/F (CPU READ/WRITE)
			CPU_VRAM_ADR		: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			CPU_VRAM_REQ		: OUT	STD_LOGIC;
			CPU_VRAM_WR			: OUT	STD_LOGIC;
			CPU_VRAM_ACK		: IN	STD_LOGIC;
			CPU_VRAM_LATCH		: IN	STD_LOGIC;
			CPU_VRAM_D			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			CPU_VRAM_Q			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			-- PALETTE MEMORY I/F (WRITE)
			PALETTE_ADR			: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			PALETTE_REQ			: OUT	STD_LOGIC;
			PALETTE_DBO			: OUT	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
			-- ACTION
			CLR_HORZ_INT		: OUT	STD_LOGIC;
			CLR_VERT_INT		: OUT	STD_LOGIC;
			-- STATUS REGISTERS
			S_F					: IN	STD_LOGIC;
			S_5S				: IN	STD_LOGIC;
			S_C					: IN	STD_LOGIC;
			S_5TH_SP			: IN	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
			S_LPS				: IN	STD_LOGIC;
			S_FH				: IN	STD_LOGIC;
			S_TR				: IN	STD_LOGIC;
			S_VR				: IN	STD_LOGIC;
			S_HR				: IN	STD_LOGIC;
			S_BD				: IN	STD_LOGIC;
			S_EO				: IN	STD_LOGIC;
			S_CE				: IN	STD_LOGIC;
			S_COLUMN			: IN	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
			S_ROW				: IN	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
			S_COLOR				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			S_BX				: IN	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
			-- COMMAND REGISTERS
			REG_IE1				: OUT	STD_LOGIC;
			REG_M543			: OUT	STD_LOGIC_VECTOR(  2 DOWNTO 0 );
			REG_BL				: OUT	STD_LOGIC;
			REG_IE0				: OUT	STD_LOGIC;
			REG_M12				: OUT	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
			REG_SI				: OUT	STD_LOGIC;
			REG_MAG				: OUT	STD_LOGIC;
			REG_PAT				: OUT	STD_LOGIC_VECTOR(  6 DOWNTO 0 );
			REG_COL_L			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			REG_GEN				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			REG_SPA_L			: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			REG_SPG				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			REG_BD				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			REG_TP				: OUT	STD_LOGIC;
			REG_SPD				: OUT	STD_LOGIC;
			REG_LN				: OUT	STD_LOGIC;
			REG_IL				: OUT	STD_LOGIC;
			REG_EO				: OUT	STD_LOGIC;
			REG_NT				: OUT	STD_LOGIC;
			REG_COL_H			: OUT	STD_LOGIC_VECTOR(  2 DOWNTO 0 );
			REG_SPA_H			: OUT	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
			REG_T2				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_BC				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_ON				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_OF				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_SPTR			: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_V				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_H				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
			REG_HIL				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			REG_DO				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			REG_CMD				: OUT	STD_LOGIC;
			REG_YAE				: OUT	STD_LOGIC;
			REG_YJK				: OUT	STD_LOGIC;
			REG_MSK				: OUT	STD_LOGIC;
			REG_SP2				: OUT	STD_LOGIC;
			REG_HO_H			: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			REG_HO_L			: OUT	STD_LOGIC_VECTOR(  2 DOWNTO 0 )
		);
	END COMPONENT;

	COMPONENT TH9958_INTERRUPT
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;

			INT_N				: OUT	STD_LOGIC;

			CLR_HORZ_INT		: IN	STD_LOGIC;
			CLR_VERT_INT		: IN	STD_LOGIC;

			UPDATE				: IN	STD_LOGIC;
			ACT_Y				: IN	STD_LOGIC;
			SCR_Y				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );

			S_F					: OUT	STD_LOGIC;
			S_FH				: OUT	STD_LOGIC;

			REG_IE0				: IN	STD_LOGIC;
			REG_IE1				: IN	STD_LOGIC;
			REG_HIL				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 )
		);
	END COMPONENT;

	COMPONENT TH9958_GRAPHIC
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;
			-- INPUT SIGNAL
			SCR_X				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			SCR_Y				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			ACT_X				: IN	STD_LOGIC;
			-- OUTPUT SIGNAL
			PALETTE				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			-- VRAM
			IL_MODE				: OUT	STD_LOGIC;
			VRAM_A				: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			VRAM_REQ			: OUT	STD_LOGIC;
			VRAM_Q				: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
			-- MODE
			SP_MODE				: OUT	STD_LOGIC;
			-- REGISTER
			REG_M543			: IN	STD_LOGIC_VECTOR(  2 DOWNTO 0 );
			REG_M12				: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
			REG_PAT				: IN	STD_LOGIC_VECTOR(  6 DOWNTO 0 );
			REG_COL_L			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			REG_GEN				: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			REG_COL_H			: IN	STD_LOGIC_VECTOR(  2 DOWNTO 0 )
		);
	END COMPONENT;

	COMPONENT TH9958_ARBITER
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;

			DRAM_PRE			: IN	STD_LOGIC;

			GRP_REQ				: IN	STD_LOGIC;
			SPR_REQ				: IN	STD_LOGIC;
			CPU_REQ				: IN	STD_LOGIC;
			CMD_REQ				: IN	STD_LOGIC;

			CPU_WR				: IN	STD_LOGIC;
			CMD_WR				: IN	STD_LOGIC;

			CPU_D				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			CMD_D				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );

			GRP_ADR				: IN	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			SPR_ADR				: IN	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			CPU_ADR				: IN	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			CMD_ADR				: IN	STD_LOGIC_VECTOR( 16 DOWNTO 0 );

			SPR_ACK				: OUT	STD_LOGIC;
			CPU_ACK				: OUT	STD_LOGIC;
			CMD_ACK				: OUT	STD_LOGIC;

			SPR_LATCH			: OUT	STD_LOGIC;
			CPU_LATCH			: OUT	STD_LOGIC;
			CMD_LATCH			: OUT	STD_LOGIC;

			IL_MODE				: IN	STD_LOGIC;

			-- DRAM INTERFACE
			DRAM_ADR			: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			DRAM_OZ				: OUT	STD_LOGIC;
			DRAM_WZ				: OUT	STD_LOGIC;
			DRAM_D				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 )
		);
	END COMPONENT;

	COMPONENT TH9958_SSG
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;
			-- OUTPUT SIGNAL
			H_CNT				: OUT	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			V_CNT				: OUT	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			RIGHT_SIDE			: OUT	STD_LOGIC;
			FIELD				: OUT	STD_LOGIC;
			-- REGISTER
			REG_PAL_MODE		: IN	STD_LOGIC;
			REG_INTERLACE_MODE	: IN	STD_LOGIC
		);
	END COMPONENT;

	COMPONENT TH9958_TG
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;
			-- SYNCHRONOUS SIGNAL
			H_CNT				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			V_CNT				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			RIGHT_SIDE			: IN	STD_LOGIC;
			FIELD				: IN	STD_LOGIC;
			-- OUTPUT SIGNAL
			HD					: OUT	STD_LOGIC;
			VD					: OUT	STD_LOGIC;
			MON_X				: OUT	STD_LOGIC_VECTOR( 10 DOWNTO 0 );
			MON_Y				: OUT	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
			SCR_X				: OUT	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			SCR_Y				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			ACT_X				: OUT	STD_LOGIC;
			ACT_Y				: OUT	STD_LOGIC;
			INTR_ACT_Y			: OUT	STD_LOGIC;
			-- REGISTER
			REG_LN				: IN	STD_LOGIC;							-- R#9  212LINE
			REG_V				: IN	STD_LOGIC_VECTOR(  3 DOWNTO 0 );	-- R#18 VERTICAL ADJUST
			REG_H				: IN	STD_LOGIC_VECTOR(  3 DOWNTO 0 );	-- R#18 HORIZONTAL ADJUST
			REG_DO				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );	-- R#23 DISPLAY OFFSET
			REG_HO_H			: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );	-- R#26 HORIZONTAL OFFSET (HIGH)
			REG_HO_L			: IN	STD_LOGIC_VECTOR(  2 DOWNTO 0 )		-- R#27 HORIZONTAL OFFSET (LOW)
		);
	END COMPONENT;

	COMPONENT TH9958_PALETTE
		PORT (
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;
			RD_A				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			RD_REQ				: IN	STD_LOGIC;
			WR_A				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			WR_REQ				: IN	STD_LOGIC;
			WR_D				: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
			RD_Q				: OUT	STD_LOGIC_VECTOR( 15 DOWNTO 0 )
		);
	END COMPONENT;

--	COMPONENT TH9958_YJK
--		PORT(
--			CLK					: IN	STD_LOGIC;
--			RESET_N				: IN	STD_LOGIC;
--			ENABLE				: IN	STD_LOGIC;
--			-- INPUT SIGNAL
--			Y					: IN	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
--			J					: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
--			K					: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
--			-- OUTPUT SIGNAL
--			R					: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
--			G					: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
--			B					: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 )
--		);
--	END COMPONENT;

	COMPONENT TH9958_SPRITE
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;

			SCR_X				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			SCR_Y				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			ACT_X				: IN	STD_LOGIC;
			ACT_Y				: IN	STD_LOGIC;

			SPR_ADR				: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			SPR_REQ				: OUT	STD_LOGIC;
			SPR_ACK				: IN	STD_LOGIC;
			SPR_LATCH			: IN	STD_LOGIC;
			SPR_Q				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );

			CLR_5S				: IN	STD_LOGIC;

			S_5S				: OUT	STD_LOGIC;
			S_5TH_SP			: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 );

			REG_MAG				: IN	STD_LOGIC;
			REG_SI				: IN	STD_LOGIC;
			REG_LN				: IN	STD_LOGIC;
			REG_SPA_L			: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			REG_SPA_H			: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );

			SP_MODE				: IN	STD_LOGIC
		);
	END COMPONENT;

	COMPONENT TH9958_VGA_UPCON
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;

			H_CNT				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			V_CNT				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			RIGHT_SIDE			: IN	STD_LOGIC;

			R					: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			G					: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			B					: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );

			VGA_R				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			VGA_G				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			VGA_B				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			VGA_HS_N			: OUT	STD_LOGIC;
			VGA_VS_N			: OUT	STD_LOGIC
		);
	END COMPONENT;

	COMPONENT TH9958_DEBUG
		PORT(
			CLK					: IN	STD_LOGIC;
			RESET_N				: IN	STD_LOGIC;
			ENABLE				: IN	STD_LOGIC;
			SCR_X				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			SCR_Y				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );

			DEBUG_R				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			DEBUG_G				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
			DEBUG_B				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );

			GRP_VRAM_ADR		: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			GRP_VRAM_REQ		: OUT	STD_LOGIC;
			GRP_VRAM_Q			: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );

			CPU_VRAM_ADR		: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
			CPU_VRAM_REQ		: OUT	STD_LOGIC;
			CPU_VRAM_WR			: OUT	STD_LOGIC;
			CPU_VRAM_ACK		: IN	STD_LOGIC;
			CPU_VRAM_LATCH		: IN	STD_LOGIC;
			CPU_VRAM_D			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			CPU_VRAM_Q			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 )
		);
	END COMPONENT;

	SIGNAL H_CNT				: STD_LOGIC_VECTOR(  9 DOWNTO 0 );
	SIGNAL V_CNT				: STD_LOGIC_VECTOR(  9 DOWNTO 0 );
	SIGNAL RIGHT_SIDE			: STD_LOGIC;
	SIGNAL VGA_R				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL VGA_G				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL VGA_B				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL VGA_HS_N				: STD_LOGIC;
	SIGNAL VGA_VS_N				: STD_LOGIC;

	SIGNAL MON_X				: STD_LOGIC_VECTOR( 10 DOWNTO 0 );
	SIGNAL MON_Y				: STD_LOGIC_VECTOR(  8 DOWNTO 0 );
	SIGNAL SCR_X				: STD_LOGIC_VECTOR(  9 DOWNTO 0 );
	SIGNAL SCR_Y				: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL GRAPHIC_VRAM_REQ		: STD_LOGIC;
	SIGNAL GRAPHIC_VRAM_ADR		: STD_LOGIC_VECTOR( 16 DOWNTO 0 );
	SIGNAL GRAPHIC_VRAM_Q		: STD_LOGIC_VECTOR( 15 DOWNTO 0 );
	SIGNAL VRAM_RD_DATA			: STD_LOGIC_VECTOR( 15 DOWNTO 0 );

	SIGNAL CPU_VRAM_ADR			: STD_LOGIC_VECTOR( 16 DOWNTO 0 );
	SIGNAL CPU_VRAM_REQ			: STD_LOGIC;
	SIGNAL CPU_VRAM_WR			: STD_LOGIC;
	SIGNAL CPU_VRAM_ACK			: STD_LOGIC;
	SIGNAL CPU_VRAM_LATCH		: STD_LOGIC;
	SIGNAL CPU_VRAM_D			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL CPU_VRAM_Q			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL CMD_VRAM_ADR			: STD_LOGIC_VECTOR( 16 DOWNTO 0 );
	SIGNAL CMD_VRAM_REQ			: STD_LOGIC;
	SIGNAL CMD_VRAM_WR			: STD_LOGIC;
	SIGNAL CMD_VRAM_ACK			: STD_LOGIC;
	SIGNAL CMD_VRAM_LATCH		: STD_LOGIC;
	SIGNAL CMD_VRAM_D			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL CMD_VRAM_Q			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL SPR_VRAM_ADR			: STD_LOGIC_VECTOR( 16 DOWNTO 0 );
	SIGNAL SPR_VRAM_REQ			: STD_LOGIC;
	SIGNAL SPR_VRAM_ACK			: STD_LOGIC;
	SIGNAL SPR_VRAM_LATCH		: STD_LOGIC;
	SIGNAL SPR_VRAM_Q			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL PALETTE_ADR			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL PALETTE_REQ			: STD_LOGIC;
	SIGNAL PALETTE_DBO			: STD_LOGIC_VECTOR( 15 DOWNTO 0 );
	SIGNAL PALETTE_DBI			: STD_LOGIC_VECTOR( 15 DOWNTO 0 );

	SIGNAL PALETTE_WR_A			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL IL_MODE				: STD_LOGIC;
	SIGNAL SP_MODE				: STD_LOGIC;

	SIGNAL PALETTE_ADRX			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL DRAM_PRE				: STD_LOGIC;

	SIGNAL CLR_HORZ_INT			: STD_LOGIC;
	SIGNAL CLR_VERT_INT			: STD_LOGIC;
	SIGNAL CLR_5S				: STD_LOGIC;
	SIGNAL INTR_UPDATE			: STD_LOGIC;
	SIGNAL ACT_X				: STD_LOGIC;
	SIGNAL ACT_Y				: STD_LOGIC;
	SIGNAL INTR_ACT_Y			: STD_LOGIC;

	SIGNAL R					: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL G					: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL B					: STD_LOGIC_VECTOR(  5 DOWNTO 0 );

	SIGNAL S_F					: STD_LOGIC;
	SIGNAL S_5S					: STD_LOGIC;
	SIGNAL S_C					: STD_LOGIC;
	SIGNAL S_5TH_SP				: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL S_LPS				: STD_LOGIC;
	SIGNAL S_FH					: STD_LOGIC;
	SIGNAL S_TR					: STD_LOGIC;
	SIGNAL S_VR					: STD_LOGIC;
	SIGNAL S_HR					: STD_LOGIC;
	SIGNAL S_BD					: STD_LOGIC;
	SIGNAL S_EO					: STD_LOGIC;
	SIGNAL S_CE					: STD_LOGIC;
	SIGNAL S_COLUMN				: STD_LOGIC_VECTOR(  8 DOWNTO 0 );
	SIGNAL S_ROW				: STD_LOGIC_VECTOR(  8 DOWNTO 0 );
	SIGNAL S_COLOR				: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL S_BX					: STD_LOGIC_VECTOR(  8 DOWNTO 0 );

	SIGNAL REG_IE1				: STD_LOGIC;
	SIGNAL REG_M543				: STD_LOGIC_VECTOR(  2 DOWNTO 0 );
	SIGNAL REG_BL				: STD_LOGIC;
	SIGNAL REG_IE0				: STD_LOGIC;
	SIGNAL REG_M12				: STD_LOGIC_VECTOR(  1 DOWNTO 0 );
	SIGNAL REG_SI				: STD_LOGIC;
	SIGNAL REG_MAG				: STD_LOGIC;
	SIGNAL REG_PAT				: STD_LOGIC_VECTOR(  6 DOWNTO 0 );
	SIGNAL REG_COL_L			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL REG_GEN				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL REG_SPA_L			: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL REG_SPG				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL REG_BD				: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL REG_TP				: STD_LOGIC;
	SIGNAL REG_SPD				: STD_LOGIC;
	SIGNAL REG_LN				: STD_LOGIC;
	SIGNAL REG_IL				: STD_LOGIC;
	SIGNAL REG_EO				: STD_LOGIC;
	SIGNAL REG_NT				: STD_LOGIC;
	SIGNAL REG_COL_H			: STD_LOGIC_VECTOR(  2 DOWNTO 0 );
	SIGNAL REG_SPA_H			: STD_LOGIC_VECTOR(  1 DOWNTO 0 );
	SIGNAL REG_T2				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_BC				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_ON				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_OF				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_SPTR				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_V				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_H				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL REG_HIL				: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL REG_DO				: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL REG_CMD				: STD_LOGIC;
	SIGNAL REG_YAE				: STD_LOGIC;
	SIGNAL REG_YJK				: STD_LOGIC;
	SIGNAL REG_MSK				: STD_LOGIC;
	SIGNAL REG_SP2				: STD_LOGIC;
	SIGNAL REG_HO_H				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL REG_HO_L				: STD_LOGIC_VECTOR(  2 DOWNTO 0 );

	SIGNAL DEBUG_R				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL DEBUG_G				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL DEBUG_B				: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
BEGIN

	VIDEO_R				<= VGA_R				;
	VIDEO_G				<= VGA_G				;
	VIDEO_B				<= VGA_B				;
	VIDEO_HS_N			<= VGA_HS_N				;
	VIDEO_VS_N			<= VGA_VS_N				;

	VIDEO_CS_N			<= '1';							-- test

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			DRAM_PRE <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF(    SCR_X( 1 DOWNTO 0 ) = "00" )THEN
				DRAM_PRE <= '1';
			ELSE
				DRAM_PRE <= '0';
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			VIDEO_DL_CLK <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF(    SCR_X( 1 DOWNTO 0 ) = "01" )THEN
				VIDEO_DL_CLK <= '1';
			ELSIF( SCR_X( 1 DOWNTO 0 ) = "11" )THEN
				VIDEO_DL_CLK <= '0';
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			VIDEO_DH_CLK <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			VIDEO_DH_CLK <= SCR_X(0);
		END IF;
	END PROCESS;

	S_C					<= '0';
	S_LPS				<= '0';
	S_TR				<= '1';
	S_BD				<= '1';
	S_CE				<= '0';
	S_COLUMN			<= (OTHERS => '0');
	S_ROW				<= (OTHERS => '0');
	S_COLOR				<= (OTHERS => '0');
	S_BX				<= (OTHERS => '0');

	---------------------------------------------------------------------------
	-- REGISTER
	---------------------------------------------------------------------------
	U_REGISTER: TH9958_REGISTER
	PORT MAP (
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,

		ADR					=> ADR					,
		REQ					=> REQ					,
		ACK					=> ACK					,
		WRT					=> WRT					,
		DBI					=> DBI					,
		DBO					=> DBO					,

		CPU_VRAM_ADR		=> CPU_VRAM_ADR			,	--OPEN					,
		CPU_VRAM_REQ		=> OPEN					,	--OPEN					,
		CPU_VRAM_WR			=> CPU_VRAM_WR			,	--OPEN					,
		CPU_VRAM_ACK		=> CPU_VRAM_ACK			,	--'0'					,
		CPU_VRAM_LATCH		=> CPU_VRAM_LATCH		,	--'0'					,
		CPU_VRAM_D			=> CPU_VRAM_D			,	--OPEN					,
		CPU_VRAM_Q			=> CPU_VRAM_Q			,	--"00000000"			,

		PALETTE_ADR			=> PALETTE_ADR			,
		PALETTE_REQ			=> PALETTE_REQ			,
		PALETTE_DBO			=> PALETTE_DBO			,

		CLR_HORZ_INT		=> CLR_HORZ_INT			,
		CLR_VERT_INT		=> CLR_VERT_INT			,

		S_F					=> S_F					,
		S_5S				=> S_5S					,
		S_C					=> S_C					,
		S_5TH_SP			=> S_5TH_SP				,
		S_LPS				=> S_LPS				,
		S_FH				=> S_FH					,
		S_TR				=> S_TR					,
		S_VR				=> S_VR					,
		S_HR				=> S_HR					,
		S_BD				=> S_BD					,
		S_EO				=> S_EO					,
		S_CE				=> S_CE					,
		S_COLUMN			=> S_COLUMN				,
		S_ROW				=> S_ROW				,
		S_COLOR				=> S_COLOR				,
		S_BX				=> S_BX					,

		REG_IE1				=> REG_IE1				,
		REG_M543			=> REG_M543				,
		REG_BL				=> REG_BL				,
		REG_IE0				=> REG_IE0				,
		REG_M12				=> REG_M12				,
		REG_SI				=> REG_SI				,
		REG_MAG				=> REG_MAG				,
		REG_PAT				=> REG_PAT				,
		REG_COL_L			=> REG_COL_L			,
		REG_GEN				=> REG_GEN				,
		REG_SPA_L			=> REG_SPA_L			,
		REG_SPG				=> REG_SPG				,
		REG_BD				=> REG_BD				,
		REG_TP				=> REG_TP				,
		REG_SPD				=> REG_SPD				,
		REG_LN				=> REG_LN				,
		REG_IL				=> REG_IL				,
		REG_EO				=> REG_EO				,
		REG_NT				=> REG_NT				,
		REG_COL_H			=> REG_COL_H			,
		REG_SPA_H			=> REG_SPA_H			,
		REG_T2				=> REG_T2				,
		REG_BC				=> REG_BC				,
		REG_ON				=> REG_ON				,
		REG_OF				=> REG_OF				,
		REG_SPTR			=> REG_SPTR				,
		REG_V				=> REG_V				,
		REG_H				=> REG_H				,
		REG_HIL				=> REG_HIL				,
		REG_DO				=> REG_DO				,
		REG_CMD				=> REG_CMD				,
		REG_YAE				=> REG_YAE				,
		REG_YJK				=> REG_YJK				,
		REG_MSK				=> REG_MSK				,
		REG_SP2				=> REG_SP2				,
		REG_HO_H			=> REG_HO_H				,
		REG_HO_L			=> REG_HO_L				
	);

	CPU_VRAM_REQ <= '1' WHEN( SCR_X( 5 DOWNTO 0 ) = "000101" )ELSE '0';

	---------------------------------------------------------------------------
	-- INTERRUPT CONTROLLER
	---------------------------------------------------------------------------
	U_INTERRUPT: TH9958_INTERRUPT
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,

		INT_N				=> INTR_N				,

		CLR_HORZ_INT		=> CLR_HORZ_INT			,
		CLR_VERT_INT		=> CLR_VERT_INT			,

		UPDATE				=> INTR_UPDATE			,
		ACT_Y				=> INTR_ACT_Y			,
		SCR_Y				=> SCR_Y				,

		S_F					=> S_F					,
		S_FH				=> S_FH					,

		REG_IE0				=> REG_IE0				,
		REG_IE1				=> REG_IE1				,
		REG_HIL				=> REG_HIL				
	);

	INTR_UPDATE <= '1' WHEN( H_CNT = 30 )ELSE '0';

	---------------------------------------------------------------------------
	-- VRAM ACCESS ARBITER
	---------------------------------------------------------------------------
	U_ARBITER: TH9958_ARBITER
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,

		DRAM_PRE			=> DRAM_PRE				,

		GRP_REQ				=> GRAPHIC_VRAM_REQ		,
		SPR_REQ				=> SPR_VRAM_REQ			,
		CPU_REQ				=> CPU_VRAM_REQ			,
		CMD_REQ				=> CMD_VRAM_REQ			,

		CPU_WR				=> CPU_VRAM_WR			,
		CMD_WR				=> CMD_VRAM_WR			,

		CPU_D				=> CPU_VRAM_D			,
		CMD_D				=> CMD_VRAM_D			,

		GRP_ADR				=> GRAPHIC_VRAM_ADR		,
		SPR_ADR				=> SPR_VRAM_ADR			,
		CPU_ADR				=> CPU_VRAM_ADR			,
		CMD_ADR				=> CMD_VRAM_ADR			,

		SPR_ACK				=> SPR_VRAM_ACK			,
		CPU_ACK				=> CPU_VRAM_ACK			,
		CMD_ACK				=> CMD_VRAM_ACK			,

		SPR_LATCH			=> SPR_VRAM_LATCH		,
		CPU_LATCH			=> CPU_VRAM_LATCH		,
		CMD_LATCH			=> CMD_VRAM_LATCH		,

		IL_MODE				=> IL_MODE				,

		DRAM_ADR			=> DRAM_A				,
		DRAM_OZ				=> DRAM_OE_N			,
		DRAM_WZ				=> DRAM_WE_N			,
		DRAM_D				=> DRAM_D				
	);

	VRAM_RD_DATA	<= DRAM_Q;
	CPU_VRAM_Q		<= VRAM_RD_DATA(  7 DOWNTO 0 );
	CMD_VRAM_Q		<= VRAM_RD_DATA(  7 DOWNTO 0 );
	SPR_VRAM_Q		<= VRAM_RD_DATA(  7 DOWNTO 0 );
	GRAPHIC_VRAM_Q	<= VRAM_RD_DATA;

	---------------------------------------------------------------------------
	-- GRAPHIC IMAGE GENERATOR
	---------------------------------------------------------------------------
	U_GRAPHIC: TH9958_GRAPHIC
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,

		SCR_X				=> SCR_X				,
		SCR_Y				=> SCR_Y				,
		ACT_X				=> ACT_X				,

		PALETTE				=> PALETTE_ADRX			,

		IL_MODE				=> IL_MODE				,
		VRAM_A				=> GRAPHIC_VRAM_ADR		,
		VRAM_REQ			=> GRAPHIC_VRAM_REQ		,
		VRAM_Q				=> GRAPHIC_VRAM_Q		,

		SP_MODE				=> SP_MODE				,

		REG_M543			=> REG_M543				,
		REG_M12				=> REG_M12				,
		REG_PAT				=> REG_PAT				,
		REG_COL_L			=> REG_COL_L			,
		REG_GEN				=> REG_GEN				,
		REG_COL_H			=> REG_COL_H			
	);

	---------------------------------------------------------------------------
	-- SYNCHRONUS SIGNAL GENERATOR
	---------------------------------------------------------------------------
	U_SSG: TH9958_SSG
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,
		H_CNT				=> H_CNT				,
		V_CNT				=> V_CNT				,
		RIGHT_SIDE			=> RIGHT_SIDE			,
		FIELD				=> S_EO					,
		REG_PAL_MODE		=> REG_NT				,
		REG_INTERLACE_MODE	=> REG_IL				
	);

	---------------------------------------------------------------------------
	-- TIMING GENERATOR
	---------------------------------------------------------------------------
	U_TG: TH9958_TG
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,
		H_CNT				=> H_CNT				,
		V_CNT				=> V_CNT				,
		RIGHT_SIDE			=> RIGHT_SIDE			,
		FIELD				=> S_EO					,
		HD					=> S_HR					,
		VD					=> S_VR					,
		MON_X				=> MON_X				,
		MON_Y				=> MON_Y				,
		SCR_X				=> SCR_X				,
		SCR_Y				=> SCR_Y				,
		ACT_X				=> ACT_X				,
		ACT_Y				=> ACT_Y				,
		INTR_ACT_Y			=> INTR_ACT_Y			,
		REG_LN				=> REG_LN				,
		REG_V				=> REG_V				,
		REG_H				=> REG_H				,
		REG_DO				=> REG_DO				,
		REG_HO_H			=> REG_HO_H				,
		REG_HO_L			=> REG_HO_L				
	);

	---------------------------------------------------------------------------
	-- PALETTE REGISTER
	---------------------------------------------------------------------------
	U_PALETTE: TH9958_PALETTE
	PORT MAP(
		CLK					=> CLK							,
		RESET_N				=> RESET_N						,
		ENABLE				=> ENABLE						,
		RD_A				=> PALETTE_ADRX					,
		RD_REQ				=> NOT SCR_X( 0 )				,
		WR_A				=> PALETTE_WR_A					,
		WR_REQ				=> PALETTE_REQ					,
		WR_D				=> PALETTE_DBO					,
		RD_Q				=> PALETTE_DBI					
	);
	PALETTE_WR_A <= "0000" & PALETTE_ADR;

	-- MIXER FOR TEST
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			G <= (OTHERS => '0');
			R <= (OTHERS => '0');
			B <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( (ACT_X AND ACT_Y) = '0' )THEN
				G <= (OTHERS => '1');
				R <= (OTHERS => '0');
				B <= (OTHERS => '1');
			ELSE
				G <= (PALETTE_DBI( 10 DOWNTO 8 ) & PALETTE_DBI( 10 DOWNTO 8 ));-- OR DEBUG_G;
				R <= (PALETTE_DBI(  6 DOWNTO 4 ) & PALETTE_DBI(  6 DOWNTO 4 ));-- OR DEBUG_R;
				B <= (PALETTE_DBI(  2 DOWNTO 0 ) & PALETTE_DBI(  2 DOWNTO 0 ));-- OR DEBUG_B;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- SPRITE
	---------------------------------------------------------------------------
	U_SPRITE: TH9958_SPRITE
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,

		SCR_X				=> SCR_X				,
		SCR_Y				=> SCR_Y				,
		ACT_X				=> ACT_X				,
		ACT_Y				=> ACT_Y				,

		SPR_ADR				=> SPR_VRAM_ADR			,
		SPR_REQ				=> SPR_VRAM_REQ			,
		SPR_ACK				=> SPR_VRAM_ACK			,
		SPR_LATCH			=> SPR_VRAM_LATCH		,
		SPR_Q				=> SPR_VRAM_Q			,

		CLR_5S				=> CLR_5S				,

		S_5S				=> S_5S					,
		S_5TH_SP			=> S_5TH_SP				,

		REG_MAG				=> REG_MAG				,
		REG_SI				=> REG_SI				,
		REG_LN				=> REG_LN				,
		REG_SPA_L			=> REG_SPA_L			,
		REG_SPA_H			=> REG_SPA_H			,

		SP_MODE				=> SP_MODE				
	);

	---------------------------------------------------------------------------
	-- NTSC TO VGA
	---------------------------------------------------------------------------
	U_VGA_UPCON: TH9958_VGA_UPCON
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,

		H_CNT				=> H_CNT				,
		V_CNT				=> V_CNT				,
		RIGHT_SIDE			=> RIGHT_SIDE			,

		R					=> R					,
		G					=> G					,
		B					=> B					,

		VGA_R				=> VGA_R				,
		VGA_G				=> VGA_G				,
		VGA_B				=> VGA_B				,
		VGA_HS_N			=> VGA_HS_N				,
		VGA_VS_N			=> VGA_VS_N				
	);

	U_DEBUG: TH9958_DEBUG
	PORT MAP(
		CLK					=> CLK					,
		RESET_N				=> RESET_N				,
		ENABLE				=> ENABLE				,
		SCR_X				=> SCR_X				,
		SCR_Y				=> SCR_Y				,

		DEBUG_R				=> DEBUG_R				,
		DEBUG_G				=> DEBUG_G				,
		DEBUG_B				=> DEBUG_B				,

		GRP_VRAM_ADR		=> OPEN					,--GRAPHIC_VRAM_ADR		,
		GRP_VRAM_REQ		=> OPEN					,--GRAPHIC_VRAM_REQ		,
		GRP_VRAM_Q			=> GRAPHIC_VRAM_Q		,

		CPU_VRAM_ADR		=> CMD_VRAM_ADR			,
		CPU_VRAM_REQ		=> OPEN					,--CMD_VRAM_REQ			,
		CPU_VRAM_WR			=> OPEN					,--CMD_VRAM_WR			,
		CPU_VRAM_ACK		=> CMD_VRAM_ACK			,
		CPU_VRAM_LATCH		=> CMD_VRAM_LATCH		,
		CPU_VRAM_D			=> CMD_VRAM_D			,
		CPU_VRAM_Q			=> CMD_VRAM_Q			
	);
	CMD_VRAM_REQ	<= '0';
	CMD_VRAM_WR		<= '0';
END RTL;