------------------------------------------------------------------------------- -- th9958_debug.vhd -- debug tool for TH9958 -- -- Copyright (C) 2008 Takayuki Hara -- All rights reserved. ------------------------------------------------------------------------------- -- -- Redistribution and use of this software or any derivative works, -- are permitted provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- 3. Redistributions may not be sold, nor may they be used in a -- commercial product or activity without specific prior written -- permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY TH9958_DEBUG IS PORT( CLK : IN STD_LOGIC; RESET_N : IN STD_LOGIC; ENABLE : IN STD_LOGIC; SCR_X : IN STD_LOGIC_VECTOR( 9 DOWNTO 0 ); SCR_Y : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); DEBUG_R : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0 ); DEBUG_G : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0 ); DEBUG_B : OUT STD_LOGIC_VECTOR( 5 DOWNTO 0 ); GRP_VRAM_ADR : OUT STD_LOGIC_VECTOR( 16 DOWNTO 0 ); GRP_VRAM_REQ : OUT STD_LOGIC; GRP_VRAM_Q : IN STD_LOGIC_VECTOR( 15 DOWNTO 0 ); CPU_VRAM_ADR : OUT STD_LOGIC_VECTOR( 16 DOWNTO 0 ); CPU_VRAM_REQ : OUT STD_LOGIC; CPU_VRAM_WR : OUT STD_LOGIC; CPU_VRAM_ACK : IN STD_LOGIC; CPU_VRAM_LATCH : IN STD_LOGIC; CPU_VRAM_D : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ); CPU_VRAM_Q : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ); END TH9958_DEBUG; ARCHITECTURE RTL OF TH9958_DEBUG IS TYPE FONT_ROM IS ARRAY( 0 TO 127 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 ); CONSTANT FONT_DATA : FONT_ROM := ( -- 0 "00111000", "01000100", "10001010", "10010010", "10100010", "01000100", "00111000", "00000000", -- 1 "00010000", "00110000", "00010000", "00010000", "00010000", "00010000", "00111000", "00000000", -- 2 "01111100", "10000010", "00000010", "00001100", "00110000", "01000000", "11111110", "00000000", -- 3 "01111100", "10000010", "00000010", "00111100", "00000010", "10000010", "01111100", "00000000", -- 4 "00011000", "00101000", "01001000", "10001000", "10001000", "11111110", "00001000", "00000000", -- 5 "11111110", "10000000", "10000000", "11111100", "00000010", "00000010", "11111100", "00000000", -- 6 "00111100", "01000000", "10000000", "11111100", "10000010", "10000010", "01111100", "00000000", -- 7 "11111110", "10000010", "00000100", "00001000", "00010000", "00010000", "00010000", "00000000", -- 8 "01111100", "10000010", "10000010", "01111100", "10000010", "10000010", "01111100", "00000000", -- 9 "01111100", "10000010", "10000010", "01111110", "00000010", "00000100", "01111000", "00000000", -- A "00010000", "00101000", "01000100", "10000010", "10000010", "11111110", "10000010", "00000000", -- B "11111100", "10000010", "10000010", "11111100", "10000010", "10000010", "11111100", "00000000", -- C "00111100", "01000010", "10000000", "10000000", "10000000", "01000010", "00111100", "00000000", -- D "11111000", "10000100", "10000010", "10000010", "10000010", "10000100", "11111000", "00000000", -- E "11111110", "10000000", "10000000", "11111100", "10000000", "10000000", "11111110", "00000000", -- F "11111110", "10000000", "10000000", "11111100", "10000000", "10000000", "10000000", "00000000" ); TYPE T_PAT_RAM IS ARRAY( 0 TO 31 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL PAT_RAM : T_PAT_RAM := ( X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00" ); SIGNAL W_ADR : STD_LOGIC_VECTOR( 6 DOWNTO 0 ); SIGNAL W_PATTERN : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL W_PAT : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL W_BIT : STD_LOGIC; SIGNAL FF_DEBUG_R : STD_LOGIC; SIGNAL FF_DEBUG_G : STD_LOGIC; SIGNAL FF_DEBUG_B : STD_LOGIC; SIGNAL FF_CNT : STD_LOGIC_VECTOR( 3 DOWNTO 0 ); SIGNAL FF_STATE : STD_LOGIC_VECTOR( 4 DOWNTO 0 ); BEGIN DEBUG_R <= (OTHERS => FF_DEBUG_R); DEBUG_G <= (OTHERS => FF_DEBUG_G); DEBUG_B <= (OTHERS => FF_DEBUG_B); W_PAT <= PAT_RAM( CONV_INTEGER(SCR_X( 9 DOWNTO 5 )) ); W_ADR <= W_PAT( 3 DOWNTO 0 ) & SCR_Y( 2 DOWNTO 0 ); W_PATTERN <= FONT_DATA( CONV_INTEGER( W_ADR ) ); WITH SCR_X( 4 DOWNTO 2 ) SELECT W_BIT <= W_PATTERN(7) WHEN "000", W_PATTERN(6) WHEN "001", W_PATTERN(5) WHEN "010", W_PATTERN(4) WHEN "011", W_PATTERN(3) WHEN "100", W_PATTERN(2) WHEN "101", W_PATTERN(1) WHEN "110", W_PATTERN(0) WHEN "111", 'X' WHEN OTHERS; PROCESS( RESET_N, CLK ) BEGIN IF( RESET_N = '0' )THEN FF_DEBUG_R <= '0'; FF_DEBUG_G <= '0'; FF_DEBUG_B <= '0'; ELSIF( CLK'EVENT AND CLK = '1' )THEN IF( ENABLE = '1' )THEN FF_DEBUG_R <= W_PAT(6) AND W_BIT; FF_DEBUG_G <= W_PAT(5) AND W_BIT; FF_DEBUG_B <= W_PAT(4) AND W_BIT; END IF; END IF; END PROCESS; -- test circuit ---------------------------------------------------------- PROCESS( RESET_N, CLK ) BEGIN IF( RESET_N = '0' )THEN CPU_VRAM_REQ <= '0'; CPU_VRAM_WR <= '0'; CPU_VRAM_ADR <= (OTHERS => '0'); CPU_VRAM_D <= (OTHERS => '0'); FF_STATE <= (OTHERS => '0'); FF_CNT <= (OTHERS => '0'); GRP_VRAM_ADR <= (OTHERS => '0'); GRP_VRAM_REQ <= '0'; ELSIF( CLK'EVENT AND CLK = '1' )THEN CASE FF_STATE IS -- WRITE PHASE WHEN "00000" => CPU_VRAM_REQ <= '1'; CPU_VRAM_WR <= '1'; CPU_VRAM_D <= "0000" & FF_CNT; CPU_VRAM_ADR <= "0000000000000" & FF_CNT; FF_STATE <= FF_STATE + 1; WHEN "00001" => IF( CPU_VRAM_ACK = '1' )THEN CPU_VRAM_REQ <= '0'; CPU_VRAM_WR <= '0'; CPU_VRAM_D <= (OTHERS => '0'); CPU_VRAM_ADR <= (OTHERS => '0'); FF_STATE <= FF_STATE + 1; END IF; WHEN "00010" => FF_CNT <= FF_CNT + 1; IF( FF_CNT = "1111" )THEN FF_STATE <= FF_STATE + 1; ELSE FF_STATE <= (OTHERS => '0'); END IF; -- READ PHASE WHEN "00011" => CPU_VRAM_REQ <= '1'; CPU_VRAM_WR <= '0'; CPU_VRAM_ADR <= "0000000000000" & FF_CNT; FF_STATE <= FF_STATE + 1; WHEN "00100" => IF( CPU_VRAM_ACK = '1' )THEN CPU_VRAM_REQ <= '0'; CPU_VRAM_ADR <= (OTHERS => '0'); FF_STATE <= FF_STATE + 1; END IF; WHEN "00101" => IF( CPU_VRAM_LATCH = '1' )THEN PAT_RAM( CONV_INTEGER( FF_CNT & '0' ) ) <= "0110" & CPU_VRAM_Q( 7 DOWNTO 4 ); PAT_RAM( CONV_INTEGER( FF_CNT & '1' ) ) <= "0110" & CPU_VRAM_Q( 3 DOWNTO 0 ); FF_STATE <= FF_STATE + 1; END IF; WHEN "00110" => FF_CNT <= FF_CNT + 1; IF( FF_CNT = "1111" )THEN FF_STATE <= "00000"; ELSE FF_STATE <= "00011"; END IF; WHEN OTHERS => FF_STATE <= "00000"; END CASE; END IF; END PROCESS; END RTL;