-------------------------------------------------------------------------------
--  th9958_interrupt.vhd
--  interrupt manager
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;
	USE WORK.TH9958_CONFIG.ALL;

ENTITY TH9958_INTERRUPT IS
	PORT(
		CLK					: IN	STD_LOGIC;
		RESET_N				: IN	STD_LOGIC;
		ENABLE				: IN	STD_LOGIC;

		INT_N				: OUT	STD_LOGIC;

		CLR_HORZ_INT		: IN	STD_LOGIC;
		CLR_VERT_INT		: IN	STD_LOGIC;

		UPDATE				: IN	STD_LOGIC;
		ACT_Y				: IN	STD_LOGIC;
		SCR_Y				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );

		S_F					: OUT	STD_LOGIC;
		S_FH				: OUT	STD_LOGIC;

		REG_IE0				: IN	STD_LOGIC;
		REG_IE1				: IN	STD_LOGIC;
		REG_HIL				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 )
	);
END TH9958_INTERRUPT;

ARCHITECTURE RTL OF TH9958_INTERRUPT IS
	SIGNAL FF_INT_N			: STD_LOGIC;
	SIGNAL FF_VERT_INT		: STD_LOGIC;
	SIGNAL FF_HORZ_INT		: STD_LOGIC;
BEGIN

	INT_N	<= FF_INT_N;
	S_F		<= FF_VERT_INT;
	S_FH	<= FF_HORZ_INT;

	---------------------------------------------------------------------------
	-- MIXED INTERRUPT SIGNAL
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_INT_N <= '1';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				FF_INT_N <= NOT ((FF_VERT_INT AND REG_IE0) OR (FF_HORZ_INT AND REG_IE1));
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- HORIZONTAL INTERRUPT SIGNAL
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_HORZ_INT <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( CLR_HORZ_INT = '1' )THEN
					FF_HORZ_INT <= '0';
				ELSIF( UPDATE = '1' AND ACT_Y = '1' AND SCR_Y = REG_HIL )THEN
					FF_HORZ_INT <= '1';
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- VERTICAL INTERRUPT SIGNAL
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VERT_INT <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( CLR_VERT_INT = '1' )THEN
					FF_VERT_INT <= '0';
				ELSIF( UPDATE = '1' AND ACT_Y = '1' AND SCR_Y = C_VERT_INT_LINE )THEN
					FF_VERT_INT <= '1';
				END IF;
			END IF;
		END IF;
	END PROCESS;
END RTL;