-------------------------------------------------------------------------------
--  th9958_linebuf_ram.vhd
--  line image buffer ram for upconverter
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- 1READ/WRITE 2BIT TYPE ------------------------------------------------------
ENTITY TH9958_LINEBUF_RAM_SUB2 IS
	PORT (
		CLK			: IN	STD_LOGIC;
		RAM_A		: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
		RAM_WE		: IN	STD_LOGIC;
		RAM_D		: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
		RAM_Q		: OUT	STD_LOGIC_VECTOR(  1 DOWNTO 0 )
	);
END TH9958_LINEBUF_RAM_SUB2;

ARCHITECTURE RTL OF TH9958_LINEBUF_RAM_SUB2 IS
	-- MEMO: OPTIMAIZED FOR FPGA DEVICE
	TYPE RAM_ARRAY IS ARRAY ( 0 TO 1023 ) OF STD_LOGIC_VECTOR(  1 DOWNTO 0 );
	SIGNAL LINEBUF_RAM	: RAM_ARRAY;
BEGIN

	PROCESS( CLK )
	BEGIN
		IF( CLK'EVENT AND CLK ='1' )THEN
			IF( RAM_WE = '1' )THEN
				LINEBUF_RAM( CONV_INTEGER(RAM_A) ) <= RAM_D;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( CLK )
	BEGIN
		IF( CLK'EVENT AND CLK ='1' )THEN
			IF( RAM_WE = '1' )THEN
				RAM_Q <= (OTHERS => '-');
			ELSE
				RAM_Q <= LINEBUF_RAM( CONV_INTEGER(RAM_A) );
			END IF;
		END IF;
	END PROCESS;
END RTL;

-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

-- 1READ/WRITE 8BIT TYPE ------------------------------------------------------
ENTITY TH9958_LINEBUF_RAM_SUB8 IS
	PORT (
		CLK			: IN	STD_LOGIC;
		RAM_A		: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
		RAM_WE		: IN	STD_LOGIC;
		RAM_D		: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		RAM_Q		: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 )
	);
END TH9958_LINEBUF_RAM_SUB8;

ARCHITECTURE RTL OF TH9958_LINEBUF_RAM_SUB8 IS
	-- MEMO: OPTIMAIZED FOR FPGA DEVICE
	TYPE RAM_ARRAY IS ARRAY ( 0 TO 1023 ) OF STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL LINEBUF_RAM	: RAM_ARRAY;
BEGIN

	PROCESS( CLK )
	BEGIN
		IF( CLK'EVENT AND CLK ='1' )THEN
			IF( RAM_WE = '1' )THEN
				LINEBUF_RAM( CONV_INTEGER(RAM_A) ) <= RAM_D;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( CLK )
	BEGIN
		IF( CLK'EVENT AND CLK ='1' )THEN
			IF( RAM_WE = '1' )THEN
				RAM_Q <= (OTHERS => '-');
			ELSE
				RAM_Q <= LINEBUF_RAM( CONV_INTEGER(RAM_A) );
			END IF;
		END IF;
	END PROCESS;
END RTL;

-------------------------------------------------------------------------------
LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TH9958_LINEBUF_RAM IS
	PORT (
		CLK			: IN	STD_LOGIC;
		RAM_A		: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
		RAM_WE		: IN	STD_LOGIC;
		RAM_DR		: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		RAM_DG		: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		RAM_DB		: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		RAM_QR		: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		RAM_QG		: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		RAM_QB		: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 )
	);
END TH9958_LINEBUF_RAM;

ARCHITECTURE RTL OF TH9958_LINEBUF_RAM IS
	COMPONENT TH9958_LINEBUF_RAM_SUB2
		PORT (
			CLK			: IN	STD_LOGIC;
			RAM_A		: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			RAM_WE		: IN	STD_LOGIC;
			RAM_D		: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
			RAM_Q		: OUT	STD_LOGIC_VECTOR(  1 DOWNTO 0 )
		);
	END COMPONENT;

	COMPONENT TH9958_LINEBUF_RAM_SUB8
		PORT (
			CLK			: IN	STD_LOGIC;
			RAM_A		: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
			RAM_WE		: IN	STD_LOGIC;
			RAM_D		: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			RAM_Q		: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 )
		);
	END COMPONENT;

	SIGNAL W_RAM_DH		: STD_LOGIC_VECTOR( 1 DOWNTO 0 );
	SIGNAL W_RAM_DM		: STD_LOGIC_VECTOR( 7 DOWNTO 0 );
	SIGNAL W_RAM_DL		: STD_LOGIC_VECTOR( 7 DOWNTO 0 );

	SIGNAL W_RAM_QH		: STD_LOGIC_VECTOR( 1 DOWNTO 0 );
	SIGNAL W_RAM_QM		: STD_LOGIC_VECTOR( 7 DOWNTO 0 );
	SIGNAL W_RAM_QL		: STD_LOGIC_VECTOR( 7 DOWNTO 0 );
BEGIN

	W_RAM_DH <= RAM_DR( 5 DOWNTO 4 );
	W_RAM_DM <= RAM_DR( 3 DOWNTO 0 ) & RAM_DG( 5 DOWNTO 2 );
	W_RAM_DL <= RAM_DG( 1 DOWNTO 0 ) & RAM_DB( 5 DOWNTO 0 );

	U_HIGH: TH9958_LINEBUF_RAM_SUB2
	PORT MAP (
		CLK			=> CLK					,
		RAM_A		=> RAM_A				,
		RAM_WE		=> RAM_WE				,
		RAM_D		=> W_RAM_DH				,
		RAM_Q		=> W_RAM_QH				
	);

	U_MID: TH9958_LINEBUF_RAM_SUB8
	PORT MAP (
		CLK			=> CLK					,
		RAM_A		=> RAM_A				,
		RAM_WE		=> RAM_WE				,
		RAM_D		=> W_RAM_DM				,
		RAM_Q		=> W_RAM_QM				
	);

	U_LOW: TH9958_LINEBUF_RAM_SUB8
	PORT MAP (
		CLK			=> CLK					,
		RAM_A		=> RAM_A				,
		RAM_WE		=> RAM_WE				,
		RAM_D		=> W_RAM_DL				,
		RAM_Q		=> W_RAM_QL				
	);

	RAM_QR <= W_RAM_QH( 1 DOWNTO 0 ) & W_RAM_QM( 7 DOWNTO 4 );
	RAM_QG <= W_RAM_QM( 3 DOWNTO 0 ) & W_RAM_QL( 7 DOWNTO 6 );
	RAM_QB <= W_RAM_QL( 5 DOWNTO 0 );
END RTL;