-------------------------------------------------------------------------------
--  th9958_palette.vhd
--  Palette
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TH9958_PALETTE IS
	PORT (
		CLK			: IN	STD_LOGIC;
		RESET_N		: IN	STD_LOGIC;
		ENABLE		: IN	STD_LOGIC;
		RD_A		: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		RD_REQ		: IN	STD_LOGIC;
		WR_A		: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		WR_REQ		: IN	STD_LOGIC;
		WR_D		: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
		RD_Q		: OUT	STD_LOGIC_VECTOR( 15 DOWNTO 0 )
	);
END TH9958_PALETTE;

ARCHITECTURE RTL OF TH9958_PALETTE IS
	COMPONENT TH9958_PALETTE_RAM
		PORT (
			CLK			: IN	STD_LOGIC;
			RAM_A		: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
			RAM_WE		: IN	STD_LOGIC;
			RAM_D		: IN	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
			RAM_Q		: OUT	STD_LOGIC_VECTOR( 15 DOWNTO 0 )
		);
	END COMPONENT;

	SIGNAL FF_WR_A_DL	: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_WR_REQ_DL	: STD_LOGIC;
	SIGNAL FF_RAM_A		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_RAM_WE	: STD_LOGIC;
	SIGNAL FF_RAM_D		: STD_LOGIC_VECTOR( 15 DOWNTO 0 );

	SIGNAL W_00			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL W_01			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL W_02			: STD_LOGIC;
	SIGNAL W_03			: STD_LOGIC;
BEGIN

	W_00 <=	RD_A WHEN( RD_REQ = '1' )ELSE
			WR_A;
	W_01 <=	FF_WR_A_DL WHEN( FF_WR_REQ_DL = '1' )ELSE
			W_00;
	W_02 <=	WR_REQ AND (NOT RD_REQ);
	W_03 <=	WR_REQ AND      RD_REQ ;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_WR_A_DL		<= (OTHERS => '0');
			FF_WR_REQ_DL	<= '0';
			FF_RAM_A		<= (OTHERS => '0');
			FF_RAM_WE		<= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				FF_WR_A_DL		<= WR_A;
				FF_WR_REQ_DL	<= W_03;
				FF_RAM_A		<= W_01;
				FF_RAM_WE		<= W_02 OR FF_WR_REQ_DL;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_RAM_D		<= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( WR_REQ = '1' )THEN
					FF_RAM_D		<= WR_D;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	U_RAM: TH9958_PALETTE_RAM
	PORT MAP (
		CLK			=> CLK			,
		RAM_A		=> FF_RAM_A		,
		RAM_WE		=> FF_RAM_WE	,
		RAM_D		=> FF_RAM_D		,
		RAM_Q		=> RD_Q			
	);
	
END RTL;