------------------------------------------------------------------------------- -- th9958_palette_ram.vhd -- Palette RAM -- -- Copyright (C) 2008 Takayuki Hara -- All rights reserved. ------------------------------------------------------------------------------- -- -- Redistribution and use of this software or any derivative works, -- are permitted provided that the following conditions are met: -- -- 1. Redistributions of source code must retain the above copyright -- notice, this list of conditions and the following disclaimer. -- 2. Redistributions in binary form must reproduce the above -- copyright notice, this list of conditions and the following -- disclaimer in the documentation and/or other materials -- provided with the distribution. -- 3. Redistributions may not be sold, nor may they be used in a -- commercial product or activity without specific prior written -- permission. -- -- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -- POSSIBILITY OF SUCH DAMAGE. -- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- 1READ/WRITE TYPE ----------------------------------------------------------- ENTITY TH9958_PALETTE_RAM_SUB IS PORT ( CLK : IN STD_LOGIC; RAM_A : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); RAM_WE : IN STD_LOGIC; RAM_D : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); RAM_Q : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ); END TH9958_PALETTE_RAM_SUB; ARCHITECTURE RTL OF TH9958_PALETTE_RAM_SUB IS -- MEMO: OPTIMAIZED FOR FPGA DEVICE TYPE RAM_ARRAY IS ARRAY ( 0 TO 255 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL PALETTE_RAM : RAM_ARRAY; BEGIN PROCESS( CLK ) BEGIN IF( CLK'EVENT AND CLK ='1' )THEN IF( RAM_WE = '1' )THEN PALETTE_RAM( CONV_INTEGER(RAM_A) ) <= RAM_D; END IF; END IF; END PROCESS; PROCESS( CLK ) BEGIN IF( CLK'EVENT AND CLK ='1' )THEN IF( RAM_WE = '1' )THEN RAM_Q <= (OTHERS => '-'); ELSE RAM_Q <= PALETTE_RAM( CONV_INTEGER(RAM_A) ); END IF; END IF; END PROCESS; END RTL; ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY TH9958_PALETTE_RAM IS PORT ( CLK : IN STD_LOGIC; RAM_A : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); RAM_WE : IN STD_LOGIC; RAM_D : IN STD_LOGIC_VECTOR( 15 DOWNTO 0 ); RAM_Q : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 ) ); END TH9958_PALETTE_RAM; ARCHITECTURE RTL OF TH9958_PALETTE_RAM IS COMPONENT TH9958_PALETTE_RAM_SUB PORT ( CLK : IN STD_LOGIC; RAM_A : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); RAM_WE : IN STD_LOGIC; RAM_D : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 ); RAM_Q : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 ) ); END COMPONENT; SIGNAL W_RAM_QH : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); SIGNAL W_RAM_QL : STD_LOGIC_VECTOR( 7 DOWNTO 0 ); BEGIN U_HIGH: TH9958_PALETTE_RAM_SUB PORT MAP ( CLK => CLK , RAM_A => RAM_A , RAM_WE => RAM_WE , RAM_D => RAM_D( 15 DOWNTO 8 ) , RAM_Q => W_RAM_QH ); U_LOW: TH9958_PALETTE_RAM_SUB PORT MAP ( CLK => CLK , RAM_A => RAM_A , RAM_WE => RAM_WE , RAM_D => RAM_D( 7 DOWNTO 0 ) , RAM_Q => W_RAM_QL ); RAM_Q <= W_RAM_QH & W_RAM_QL; END RTL;