-------------------------------------------------------------------------------
--  th9958.vhd
--  Register for TH9958
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TH9958_REGISTER IS
	PORT(
		CLK					: IN	STD_LOGIC;
		RESET_N				: IN	STD_LOGIC;
		ENABLE				: IN	STD_LOGIC;
		-- CPU I/F
		ADR					: IN	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
		REQ					: IN	STD_LOGIC;
		ACK					: OUT	STD_LOGIC;
		WRT					: IN	STD_LOGIC;
		DBI					: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		DBO					: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		-- DRAM I/F (CPU READ/WRITE)
		CPU_VRAM_ADR		: OUT	STD_LOGIC_VECTOR( 16 DOWNTO 0 );
		CPU_VRAM_REQ		: OUT	STD_LOGIC;
		CPU_VRAM_WR			: OUT	STD_LOGIC;
		CPU_VRAM_ACK		: IN	STD_LOGIC;
		CPU_VRAM_LATCH		: IN	STD_LOGIC;
		CPU_VRAM_D			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		CPU_VRAM_Q			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		-- PALETTE MEMORY I/F (WRITE)
		PALETTE_ADR			: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		PALETTE_REQ			: OUT	STD_LOGIC;
		PALETTE_DBO			: OUT	STD_LOGIC_VECTOR( 15 DOWNTO 0 );
		-- ACTION
		CLR_HORZ_INT		: OUT	STD_LOGIC;
		CLR_VERT_INT		: OUT	STD_LOGIC;
		CLR_5S				: OUT	STD_LOGIC;
		-- STATUS REGISTERS
		S_F					: IN	STD_LOGIC;
		S_5S				: IN	STD_LOGIC;
		S_C					: IN	STD_LOGIC;
		S_5TH_SP			: IN	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
		S_LPS				: IN	STD_LOGIC;
		S_FH				: IN	STD_LOGIC;
		S_TR				: IN	STD_LOGIC;
		S_VR				: IN	STD_LOGIC;
		S_HR				: IN	STD_LOGIC;
		S_BD				: IN	STD_LOGIC;
		S_EO				: IN	STD_LOGIC;
		S_CE				: IN	STD_LOGIC;
		S_COLUMN			: IN	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
		S_ROW				: IN	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
		S_COLOR				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		S_BX				: IN	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
		-- COMMAND REGISTERS
		REG_IE1				: OUT	STD_LOGIC;
		REG_M543			: OUT	STD_LOGIC_VECTOR(  2 DOWNTO 0 );
		REG_BL				: OUT	STD_LOGIC;
		REG_IE0				: OUT	STD_LOGIC;
		REG_M12				: OUT	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
		REG_SI				: OUT	STD_LOGIC;
		REG_MAG				: OUT	STD_LOGIC;
		REG_PAT				: OUT	STD_LOGIC_VECTOR(  6 DOWNTO 0 );
		REG_COL_L			: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		REG_GEN				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		REG_SPA_L			: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		REG_SPG				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		REG_BD				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		REG_TP				: OUT	STD_LOGIC;
		REG_SPD				: OUT	STD_LOGIC;
		REG_LN				: OUT	STD_LOGIC;
		REG_IL				: OUT	STD_LOGIC;
		REG_EO				: OUT	STD_LOGIC;
		REG_NT				: OUT	STD_LOGIC;
		REG_COL_H			: OUT	STD_LOGIC_VECTOR(  2 DOWNTO 0 );
		REG_SPA_H			: OUT	STD_LOGIC_VECTOR(  1 DOWNTO 0 );
		REG_T2				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_BC				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_ON				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_OF				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_SPTR			: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_V				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_H				: OUT	STD_LOGIC_VECTOR(  3 DOWNTO 0 );
		REG_HIL				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		REG_DO				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		REG_CMD				: OUT	STD_LOGIC;
		REG_YAE				: OUT	STD_LOGIC;
		REG_YJK				: OUT	STD_LOGIC;
		REG_MSK				: OUT	STD_LOGIC;
		REG_SP2				: OUT	STD_LOGIC;
		REG_HO_H			: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		REG_HO_L			: OUT	STD_LOGIC_VECTOR(  2 DOWNTO 0 )
	);
END TH9958_REGISTER;

ARCHITECTURE RTL OF TH9958_REGISTER IS
	SIGNAL FF_IE1			: STD_LOGIC;
	SIGNAL FF_M543			: STD_LOGIC_VECTOR(  2 DOWNTO 0 );
	SIGNAL FF_BL			: STD_LOGIC;
	SIGNAL FF_IE0			: STD_LOGIC;
	SIGNAL FF_M12			: STD_LOGIC_VECTOR(  1 DOWNTO 0 );
	SIGNAL FF_SI			: STD_LOGIC;
	SIGNAL FF_MAG			: STD_LOGIC;
	SIGNAL FF_PAT			: STD_LOGIC_VECTOR(  6 DOWNTO 0 );
	SIGNAL FF_COL_L			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_GEN			: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_SPA_L			: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_SPG			: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_BD			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_TP			: STD_LOGIC;
	SIGNAL FF_SPD			: STD_LOGIC;
	SIGNAL FF_LN			: STD_LOGIC;
	SIGNAL FF_IL			: STD_LOGIC;
	SIGNAL FF_EO			: STD_LOGIC;
	SIGNAL FF_NT			: STD_LOGIC;
	SIGNAL FF_COL_H			: STD_LOGIC_VECTOR(  2 DOWNTO 0 );
	SIGNAL FF_SPA_H			: STD_LOGIC_VECTOR(  1 DOWNTO 0 );
	SIGNAL FF_T2			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_BC			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_ON			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_OF			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_VRAM_H		: STD_LOGIC_VECTOR(  2 DOWNTO 0 );
	SIGNAL FF_SPTR			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_PPTR			: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_AII			: STD_LOGIC;
	SIGNAL FF_RPTR			: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_V				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_H				: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_HIL			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_DO			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_CMD			: STD_LOGIC;
	SIGNAL FF_YAE			: STD_LOGIC;
	SIGNAL FF_YJK			: STD_LOGIC;
	SIGNAL FF_MSK			: STD_LOGIC;
	SIGNAL FF_SP2			: STD_LOGIC;
	SIGNAL FF_HO_H			: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_HO_L			: STD_LOGIC_VECTOR(  2 DOWNTO 0 );

	SIGNAL FF_ADR			: STD_LOGIC_VECTOR(  1 DOWNTO 0 );
	SIGNAL FF_REQ			: STD_LOGIC;
	SIGNAL FF_WRT			: STD_LOGIC;
	SIGNAL FF_DBI			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_DBO			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL FF_PORT1_LAST	: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_PORT1_STAT	: STD_LOGIC;
	SIGNAL FF_PORT2_LAST	: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_PORT2_STAT	: STD_LOGIC;

	SIGNAL FF_VRAM_L		: STD_LOGIC_VECTOR( 13 DOWNTO 0 );
	SIGNAL FF_VRAM_W		: STD_LOGIC;
	SIGNAL FF_VRAM_REQ		: STD_LOGIC;
	SIGNAL FF_VRAM_WR		: STD_LOGIC;
	SIGNAL FF_VRAM_D		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL FF_VRAM_RD		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );

	SIGNAL FF_PALETTE_ADR	: STD_LOGIC_VECTOR(  3 DOWNTO 0 );
	SIGNAL FF_PALETTE_REQ	: STD_LOGIC;
	SIGNAL FF_PALETTE_DBO	: STD_LOGIC_VECTOR( 15 DOWNTO 0 );

	SIGNAL W_PORT0			: STD_LOGIC;
	SIGNAL W_PORT1			: STD_LOGIC;
	SIGNAL W_PORT2			: STD_LOGIC;
	SIGNAL W_PORT3			: STD_LOGIC;

	SIGNAL W_VRAM_L_NEXT	: STD_LOGIC_VECTOR( 16 DOWNTO 0 );
	SIGNAL W_TMS9918		: STD_LOGIC;

	SIGNAL W_REG_WRT		: STD_LOGIC;
	SIGNAL W_REG_PTR		: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL W_REG_DAT		: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
BEGIN

	REG_IE1			<= FF_IE1		;
	REG_M543		<= FF_M543		;
	REG_BL			<= FF_BL		;
	REG_IE0			<= FF_IE0		;
	REG_M12			<= FF_M12		;
	REG_SI			<= FF_SI		;
	REG_MAG			<= FF_MAG		;
	REG_PAT			<= FF_PAT		;
	REG_COL_L		<= FF_COL_L		;
	REG_GEN			<= FF_GEN		;
	REG_SPA_L		<= FF_SPA_L		;
	REG_SPG			<= FF_SPG		;
	REG_BD			<= FF_BD		;
	REG_TP			<= FF_TP		;
	REG_SPD			<= FF_SPD		;
	REG_LN			<= FF_LN		;
	REG_IL			<= FF_IL		;
	REG_EO			<= FF_EO		;
	REG_NT			<= FF_NT		;
	REG_COL_H		<= FF_COL_H		;
	REG_SPA_H		<= FF_SPA_H		;
	REG_T2			<= FF_T2		;
	REG_BC			<= FF_BC		;
	REG_ON			<= FF_ON		;
	REG_OF			<= FF_OF		;
	REG_SPTR		<= FF_SPTR		;
	REG_V			<= FF_V			;
	REG_H			<= FF_H			;
	REG_HIL			<= FF_HIL		;
	REG_DO			<= FF_DO		;
	REG_CMD			<= FF_CMD		;
	REG_YAE			<= FF_YAE		;
	REG_YJK			<= FF_YJK		;
	REG_MSK			<= FF_MSK		;
	REG_SP2			<= FF_SP2		;
	REG_HO_H		<= FF_HO_H		;
	REG_HO_L		<= FF_HO_L		;

	DBO				<= FF_DBO;
	CPU_VRAM_REQ	<= FF_VRAM_REQ;
	CPU_VRAM_WR		<= FF_VRAM_WR;
	CPU_VRAM_ADR	<= FF_VRAM_H & FF_VRAM_L;
	CPU_VRAM_D		<= FF_VRAM_D;
	PALETTE_ADR		<= FF_PALETTE_ADR;
	PALETTE_REQ		<= FF_PALETTE_REQ;
	PALETTE_DBO		<= FF_PALETTE_DBO;

	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_ADR <= "00";
			FF_REQ <= '0';
			FF_WRT <= '0';
			FF_DBI <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				FF_ADR <= ADR;
				FF_REQ <= REQ;
				FF_WRT <= WRT;
				FF_DBI <= DBI;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- ADDRESS DECODER
	---------------------------------------------------------------------------
	W_PORT0 <= FF_REQ WHEN( FF_ADR = "00" )ELSE '0';
	W_PORT1 <= FF_REQ WHEN( FF_ADR = "01" )ELSE '0';
	W_PORT2 <= FF_REQ WHEN( FF_ADR = "10" )ELSE '0';
	W_PORT3 <= FF_REQ WHEN( FF_ADR = "11" )ELSE '0';

	---------------------------------------------------------------------------
	-- COMPATIBLE MODE DETECTOR
	---------------------------------------------------------------------------
	W_TMS9918 <= '1' WHEN(	(FF_M543 = "000" AND FF_M12 = "00") OR		-- GRAPHIC1
							(FF_M543 = "001" AND FF_M12 = "00") OR		-- GRAPHIC2
							(FF_M543 = "000" AND FF_M12 = "01") OR		-- MULTI COLOR
							(FF_M543 = "000" AND FF_M12 = "10") )ELSE	-- TEXT1
				 '0';

	---------------------------------------------------------------------------
	-- PORT#0 (READ/WRITE)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VRAM_REQ	<= '0';
			FF_VRAM_WR	<= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( W_PORT0 = '1' )THEN
				FF_VRAM_REQ	<= '1';
				FF_VRAM_WR	<= FF_WRT;
			ELSIF( CPU_VRAM_ACK = '1' )THEN
				FF_VRAM_REQ	<= '0';
				FF_VRAM_WR	<= '0';
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VRAM_D <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( W_PORT0 = '1' )THEN
				FF_VRAM_D <= FF_DBI;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- PORT#1 (WRITE)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_PORT1_STAT <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT1 = '1' AND FF_WRT = '1' )THEN
					FF_PORT1_STAT <= NOT FF_PORT1_STAT;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_PORT1_LAST <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT1 = '1' AND FF_WRT = '1' )THEN
					FF_PORT1_LAST <= FF_DBI;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VRAM_W <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT1 = '1' AND FF_WRT = '1' AND FF_PORT1_STAT = '1' AND FF_DBI(7) = '0' )THEN
					FF_VRAM_W <= FF_DBI(6);
				END IF;
			END IF;
		END IF;
	END PROCESS;

	W_VRAM_L_NEXT <= (FF_VRAM_H & FF_VRAM_L) + 1;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VRAM_L <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF(    W_PORT1 = '1' AND FF_WRT = '1' AND FF_PORT1_STAT = '1' AND FF_DBI(7) = '0' )THEN
					FF_VRAM_L(  7 DOWNTO 0 ) <= FF_PORT1_LAST;
					FF_VRAM_L( 13 DOWNTO 8 ) <= FF_DBI( 5 DOWNTO 0 );
				ELSIF( FF_VRAM_REQ = '1' AND CPU_VRAM_ACK = '1' )THEN
					FF_VRAM_L <= W_VRAM_L_NEXT( 13 DOWNTO 0 );
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- PORT#2 (WRITE)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_PORT2_STAT <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT2 = '1' AND FF_WRT = '1' )THEN
					FF_PORT2_STAT <= NOT FF_PORT2_STAT;
				ELSIF( W_REG_PTR(4 DOWNTO 0) = "10000" AND W_REG_WRT = '1' )THEN
					FF_PORT2_STAT <= '0';
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_PORT2_LAST <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT2 = '1' AND FF_WRT = '1' )THEN
					FF_PORT2_LAST <= FF_DBI;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_PALETTE_REQ <= '0';
			FF_PALETTE_ADR <= (OTHERS => '0');
			FF_PALETTE_DBO <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT2 = '1' AND FF_WRT = '1' AND FF_PORT2_STAT = '1' )THEN
					FF_PALETTE_REQ <= '1';
					FF_PALETTE_ADR <= FF_PPTR;
					FF_PALETTE_DBO <= FF_DBI & FF_PORT2_LAST;
				ELSE
					FF_PALETTE_REQ <= '0';
					FF_PALETTE_ADR <= (OTHERS => '0');
					FF_PALETTE_DBO <= (OTHERS => '0');
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- REGISTER WRITE
	---------------------------------------------------------------------------
	W_REG_PTR <= FF_RPTR	WHEN( W_PORT3 = '1' )ELSE
				 FF_DBI(5 DOWNTO 0);
	W_REG_DAT <= FF_DBI		WHEN( W_PORT3 = '1' )ELSE
				 FF_PORT1_LAST;
	W_REG_WRT <= FF_WRT AND (NOT W_REG_PTR(5)) AND (W_PORT3 OR (W_PORT1 AND FF_DBI(7) AND FF_PORT1_STAT));

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_IE1			<= '0';
			FF_M543			<= "000";
			FF_BL			<= '0';
			FF_IE0			<= '0';
			FF_M12			<= "00";
			FF_SI			<= '0';
			FF_MAG			<= '0';
			FF_PAT			<= (OTHERS => '0');
			FF_COL_L		<= (OTHERS => '0');
			FF_GEN			<= (OTHERS => '0');
			FF_SPA_L		<= (OTHERS => '0');
			FF_BD			<= (OTHERS => '0');
			FF_TP			<= '0';
			FF_SPD			<= '0';
			FF_LN			<= '0';
			FF_IL			<= '0';
			FF_EO			<= '0';
			FF_NT			<= '0';
			FF_COL_H		<= (OTHERS => '0');
			FF_SPA_H		<= (OTHERS => '0');
			FF_SPG			<= (OTHERS => '0');
			FF_T2			<= (OTHERS => '0');
			FF_BC			<= (OTHERS => '0');
			FF_ON			<= (OTHERS => '0');
			FF_OF			<= (OTHERS => '0');
			FF_SPTR			<= (OTHERS => '0');
			FF_AII			<= '0';
			FF_V			<= (OTHERS => '0');
			FF_H			<= (OTHERS => '0');
			FF_HIL			<= (OTHERS => '0');
			FF_DO			<= (OTHERS => '0');
			FF_CMD			<= '0';
			FF_YAE			<= '0';
			FF_YJK			<= '0';
			FF_MSK			<= '0';
			FF_SP2			<= '0';
			FF_HO_H			<= (OTHERS => '0');
			FF_HO_L			<= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' AND W_REG_WRT = '1' )THEN
				CASE W_REG_PTR(4 DOWNTO 0) IS
				WHEN "00000" =>		-- R#0
					FF_IE1			<= W_REG_DAT(4);
					FF_M543			<= W_REG_DAT(3 DOWNTO 1);
				WHEN "00001" =>		-- R#1
					FF_BL			<= W_REG_DAT(6);
					FF_IE0			<= W_REG_DAT(5);
					FF_M12			<= W_REG_DAT(4 DOWNTO 3);
					FF_SI			<= W_REG_DAT(1);
					FF_MAG			<= W_REG_DAT(0);
				WHEN "00010" =>		-- R#2
					FF_PAT			<= W_REG_DAT(6 DOWNTO 0);
				WHEN "00011" =>		-- R#3
					FF_COL_L		<= W_REG_DAT;
				WHEN "00100" =>		-- R#4
					FF_GEN			<= W_REG_DAT(5 DOWNTO 0);
				WHEN "00101" =>		-- R#5
					FF_SPA_L		<= W_REG_DAT(7 DOWNTO 2);
				WHEN "00110" =>		-- R#6
					FF_SPG			<= W_REG_DAT(5 DOWNTO 0);
				WHEN "00111" =>		-- R#7
					FF_BD			<= W_REG_DAT;
				WHEN "01000" =>		-- R#8
					FF_TP			<= W_REG_DAT(5);
					FF_SPD			<= W_REG_DAT(1);
				WHEN "01001" =>		-- R#9
					FF_LN			<= W_REG_DAT(7);
					FF_IL			<= W_REG_DAT(3);
					FF_EO			<= W_REG_DAT(2);
					FF_NT			<= W_REG_DAT(1);
				WHEN "01010" =>		-- R#10
					FF_COL_H		<= W_REG_DAT(2 DOWNTO 0);
				WHEN "01011" =>		-- R#11
					FF_SPA_H		<= W_REG_DAT(1 DOWNTO 0);
				WHEN "01100" =>		-- R#12
					FF_T2			<= W_REG_DAT(7 DOWNTO 4);
					FF_BC			<= W_REG_DAT(3 DOWNTO 0);
				WHEN "01101" =>		-- R#13
					FF_ON			<= W_REG_DAT(7 DOWNTO 4);
					FF_OF			<= W_REG_DAT(3 DOWNTO 0);
				WHEN "01110" =>		-- R#14
					-- FF_VRAM_H writes in a separate paragraph.
				WHEN "01111" =>		-- R#15
					FF_SPTR			<= W_REG_DAT(3 DOWNTO 0);
				WHEN "10000" =>		-- R#16
					-- FF_PPTR writes in a separate paragraph.
				WHEN "10001" =>		-- R#17
					FF_AII			<= W_REG_DAT(7);
					-- FF_RPTR writes in a separate paragraph.
				WHEN "10010" =>		-- R#18
					FF_V			<= W_REG_DAT(7 DOWNTO 4);
					FF_H			<= W_REG_DAT(3 DOWNTO 0);
				WHEN "10011" =>		-- R#19
					FF_HIL			<= W_REG_DAT;
				WHEN "10100" =>		-- R#20
					NULL;
				WHEN "10101" =>		-- R#21
					NULL;
				WHEN "10110" =>		-- R#22
					NULL;
				WHEN "10111" =>		-- R#23
					FF_DO			<= W_REG_DAT;
				WHEN "11000" =>		-- R#24
					NULL;
				WHEN "11001" =>		-- R#25
					FF_CMD			<= W_REG_DAT(6);
					FF_YAE			<= W_REG_DAT(4);
					FF_YJK			<= W_REG_DAT(3);
					FF_MSK			<= W_REG_DAT(1);
					FF_SP2			<= W_REG_DAT(0);
				WHEN "11010" =>		-- R#26
					FF_HO_H			<= W_REG_DAT(5 DOWNTO 0);
				WHEN "11011" =>		-- R#27
					FF_HO_L			<= W_REG_DAT(2 DOWNTO 0);
				WHEN OTHERS =>
					NULL;
				END CASE;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VRAM_H <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_REG_PTR(4 DOWNTO 0) = "01110" AND W_REG_WRT = '1' )THEN
					FF_VRAM_H <= W_REG_DAT(2 DOWNTO 0);
				ELSIF( FF_VRAM_REQ = '1' AND CPU_VRAM_ACK = '1' AND W_TMS9918 = '0' )THEN
					FF_VRAM_H <= W_VRAM_L_NEXT( 16 DOWNTO 14 );
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_PPTR <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_REG_PTR(4 DOWNTO 0) = "10000" AND W_REG_WRT = '1' )THEN
					FF_PPTR <= W_REG_DAT(3 DOWNTO 0);
				ELSIF( W_PORT2 = '1' AND FF_WRT = '1' AND FF_PORT2_STAT = '1' )THEN
					FF_PPTR <= FF_PPTR + 1;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_RPTR <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' AND W_REG_WRT = '1' )THEN
				IF( W_REG_PTR(4 DOWNTO 0) = "10001" )THEN
					FF_RPTR <= W_REG_DAT(5 DOWNTO 0);
				ELSIF( FF_AII = '0' )THEN
					FF_RPTR <= FF_RPTR + 1;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- REGISTER READ
	---------------------------------------------------------------------------
	ACK <= '0';

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VRAM_RD <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( CPU_VRAM_LATCH = '1' )THEN
				FF_VRAM_RD <= CPU_VRAM_Q;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_DBO <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF(    W_PORT0 = '1' AND FF_WRT = '0' )THEN	-- READ VRAM
					FF_DBO <= FF_VRAM_RD;
				ELSIF( W_PORT1 = '1' AND FF_WRT = '0' )THEN	-- READ STATUS REGISTER
					CASE FF_SPTR IS
					WHEN "0000" =>	-- S#0
						FF_DBO <= S_F & S_5S & S_C & S_5TH_SP;
					WHEN "0001" =>	-- S#1
						FF_DBO <= '0' & S_LPS & "00010" & S_FH;
					WHEN "0010" =>	-- S#2
						FF_DBO <= S_TR & S_VR & S_HR & S_BD & "11" & S_EO & S_CE;
					WHEN "0011" =>	-- S#3
						FF_DBO <= S_COLUMN( 7 DOWNTO 0 );
					WHEN "0100" =>	-- S#4
						FF_DBO <= "1111111" & S_COLUMN(8);
					WHEN "0101" =>	-- S#5
						FF_DBO <= S_ROW( 7 DOWNTO 0 );
					WHEN "0110" =>	-- S#6
						FF_DBO <= "111111" & S_EO & S_ROW(8);
					WHEN "0111" =>	-- S#7
						FF_DBO <= S_COLOR;
					WHEN "1000" =>	-- S#8
						FF_DBO <= S_BX( 7 DOWNTO 0 );
					WHEN "1001" =>	-- S#9
						FF_DBO <= "1111111" & S_BX(8);
					WHEN OTHERS =>
						FF_DBO <= (OTHERS => '0');
					END CASE;
				ELSIF( W_PORT2 = '1' OR W_PORT3 = '1' )THEN
					FF_DBO <= (OTHERS => '1');
				ELSE
					-- HOLD
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			CLR_HORZ_INT <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT1 = '1' AND FF_WRT = '0' AND FF_SPTR = "0001" )THEN	-- READ STATUS REGISTER#1
					CLR_HORZ_INT <= '1';
				ELSE
					CLR_HORZ_INT <= '0';
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			CLR_VERT_INT	<= '0';
			CLR_5S			<= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( W_PORT1 = '1' AND FF_WRT = '0' AND FF_SPTR = "0000" )THEN	-- READ STATUS REGISTER#0
					CLR_VERT_INT	<= '1';
					CLR_5S			<= '1';
				ELSE
					CLR_VERT_INT	<= '0';
					CLR_5S			<= '0';
				END IF;
			END IF;
		END IF;
	END PROCESS;
END RTL;