-------------------------------------------------------------------------------
--  th9958_sprite_delay_line.vhd
--  line image buffer ram for sprite
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TH9958_SPRITE_DELAY_LINE IS
	PORT (
		CLK			: IN	STD_LOGIC;

		ADR			: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		WE			: IN	STD_LOGIC;
		D			: IN	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
		Q			: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 )
	);
END TH9958_SPRITE_DELAY_LINE;

ARCHITECTURE RTL OF TH9958_SPRITE_DELAY_LINE IS
	TYPE RAM_ARRAY: ARRAY( 0 TO 255 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
	SIGNAL LINE_RAM: RAM_ARRAY;
	SIGNAL FF_Q : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
BEGIN

	PROCESS( CLK )
	BEGIN
		IF( CLK'EVENT AND CLK = '1' )THEN
			IF( WE = '1' )THEN
				LINE_RAM( CONV_INTEGER( ADR ) ) <= "000" & D;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( CLK )
	BEGIN
		IF( CLK'EVENT AND CLK = '1' )THEN
			IF( WE = '1' )THEN
				FF_Q <= (OTHERS => 'X');
			ELSE
				FF_Q <= LINE_RAM( CONV_INTEGER( ADR ) );
			END IF;
		END IF;
	END PROCESS;

	Q <= FF_Q( 4 DOWNTO 0 );
END RTL;