-------------------------------------------------------------------------------
--  th9958_sprite_pix.vhd
--  sprite for TH9958
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;
	USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY TH9958_SPRITE_PIX IS
	PORT(
		CLK					: IN	STD_LOGIC;
		RESET_N				: IN	STD_LOGIC;
		ENABLE				: IN	STD_LOGIC;

	--	CONTROL SIGNAL
		H_CNT				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );

	--	PIXEL
		SP_PIX_EN			: OUT	STD_LOGIC;
		SP_PIX				: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 );

	--	RAM
		RAM_D				: OUT	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		RAM_A				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		RAM_Q				: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		RAM_WE				: OUT	STD_LOGIC
	);
END TH9958_SPRITE_PIX;

ARCHITECTURE RTL OF TH9958_SPRITE_PIX IS
	SIGNAL FF_Q1		: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_Q2		: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_Q3		: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_Q4		: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_Q5		: STD_LOGIC_VECTOR(  5 DOWNTO 0 );
	SIGNAL FF_RAM_WE	: STD_LOGIC;

	SIGNAL W_DOT_PHASE	: STD_LOGIC_VECTOR(  1 DOWNTO 0 );
BEGIN

	RAM_D		<= (OTHERS => '0');
	RAM_WE		<= FF_RAM_WE;
	RAM_A		<= H_CNT( 9 DOWNTO 2 );

	SP_PIX_EN	<= FF_Q5( 5 );
	SP_PIX		<= FF_Q5( 4 DOWNTO 0 );

	W_DOT_PHASE	<= H_CNT( 1 DOWNTO 0 );

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_RAM_WE <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				FF_RAM_WE <= W_DOT_PHASE(1) AND (NOT W_DOT_PHASE(0));
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_Q1 <= (OTHERS => '0');
			FF_Q2 <= (OTHERS => '0');
			FF_Q3 <= (OTHERS => '0');
			FF_Q4 <= (OTHERS => '0');
			FF_Q5 <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( FF_RAM_WE = '1' )THEN
					FF_Q1 <= RAM_Q;
					FF_Q2 <= FF_Q1;
					FF_Q3 <= FF_Q2;
					FF_Q4 <= FF_Q3;
					FF_Q5 <= FF_Q4;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END RTL;