-------------------------------------------------------------------------------
--  th9958_tg.vhd
--  Timing Generator for TH9958
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;
	USE WORK.TH9958_CONFIG.ALL;

ENTITY TH9958_TG IS
	PORT(
		CLK					: IN	STD_LOGIC;
		RESET_N				: IN	STD_LOGIC;
		ENABLE				: IN	STD_LOGIC;
		-- SYNCHRONOUS SIGNAL
		H_CNT				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
		V_CNT				: IN	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
		RIGHT_SIDE			: IN	STD_LOGIC;
		FIELD				: IN	STD_LOGIC;
		-- OUTPUT SIGNAL
		HD					: OUT	STD_LOGIC;
		VD					: OUT	STD_LOGIC;
		MON_X				: OUT	STD_LOGIC_VECTOR( 10 DOWNTO 0 );
		MON_Y				: OUT	STD_LOGIC_VECTOR(  8 DOWNTO 0 );
		SCR_X				: OUT	STD_LOGIC_VECTOR(  9 DOWNTO 0 );
		SCR_Y				: OUT	STD_LOGIC_VECTOR(  7 DOWNTO 0 );
		ACT_X				: OUT	STD_LOGIC;
		ACT_Y				: OUT	STD_LOGIC;
		INTR_ACT_Y			: OUT	STD_LOGIC;
		-- REGISTER
		REG_LN				: IN	STD_LOGIC;							-- R#9  212LINE
		REG_V				: IN	STD_LOGIC_VECTOR(  3 DOWNTO 0 );	-- R#18 VERTICAL ADJUST
		REG_H				: IN	STD_LOGIC_VECTOR(  3 DOWNTO 0 );	-- R#18 HORIZONTAL ADJUST
		REG_DO				: IN	STD_LOGIC_VECTOR(  7 DOWNTO 0 );	-- R#23 DISPLAY OFFSET
		REG_HO_H			: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );	-- R#26 HORIZONTAL OFFSET (HIGH)
		REG_HO_L			: IN	STD_LOGIC_VECTOR(  2 DOWNTO 0 )		-- R#27 HORIZONTAL OFFSET (LOW)
	);
END TH9958_TG;

ARCHITECTURE RTL OF TH9958_TG IS
	SIGNAL FF_HD			: STD_LOGIC;
	SIGNAL FF_VD			: STD_LOGIC;
	SIGNAL FF_MON_X			: STD_LOGIC_VECTOR( 10 DOWNTO 0 );
	SIGNAL FF_MON_Y			: STD_LOGIC_VECTOR(  8 DOWNTO 0 );
	SIGNAL FF_SCR_X			: STD_LOGIC_VECTOR(  9 DOWNTO 0 );
	SIGNAL FF_SCR_Y			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL FF_ACT_X			: STD_LOGIC;
	SIGNAL FF_ACT_Y			: STD_LOGIC;
	SIGNAL FF_INTR_ACT_Y	: STD_LOGIC;
BEGIN

	-- OUTPUT ASSIGNMENT
	HD			<= FF_HD;
	VD			<= FF_VD;
	MON_X		<= FF_MON_X;
	MON_Y		<= FF_MON_Y;
	SCR_X		<= FF_SCR_X;
	SCR_Y		<= FF_SCR_Y;
	ACT_X		<= FF_ACT_X;
	ACT_Y		<= FF_ACT_Y;
	INTR_ACT_Y	<= FF_INTR_ACT_Y;

	---------------------------------------------------------------------------
	-- MONITOR X (1CLK DELAY)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_MON_X <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( RIGHT_SIDE = '1' )THEN
					FF_MON_X <= ('0' & H_CNT) + 684;
				ELSE
					FF_MON_X <= ('0' & H_CNT);
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- MONITOR Y (1CLK DELAY)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_MON_Y <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( RIGHT_SIDE = '0' AND H_CNT = 0 )THEN
					FF_MON_Y <= V_CNT( 9 DOWNTO 1 );
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- HD (1CLK DELAY)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_HD <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF(    FF_MON_X = C_H_SIZE-1 )THEN
					FF_HD <= '0';
				ELSIF( FF_MON_X =   C_HD_END-1 )THEN
					FF_HD <= '1';
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- VD (1CLK DELAY)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_VD <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( FF_MON_X = 1367 )THEN
					IF(    V_CNT = 0 )THEN
						FF_VD <= '0';
					ELSIF( V_CNT = 2 )THEN
						FF_VD <= '1';
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- SCREEN X (1CLK DELAY)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_SCR_X <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				FF_SCR_X <= FF_MON_X( 9 DOWNTO 0 ) - (240 + 41 + 18 - 1);
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- SCREEN Y (1CLK DELAY)
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_SCR_Y <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				FF_SCR_Y <= (FF_MON_Y( 7 DOWNTO 0 ) - (2 + 47 - 1)) + REG_DO;
			END IF;
		END IF;
	END PROCESS;

	---------------------------------------------------------------------------
	-- ACTIVE WINDOW
	---------------------------------------------------------------------------
	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_ACT_X <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( FF_MON_X = (240 + 41 + 18 - 1) )THEN
					FF_ACT_X <= '1';
				ELSIF( FF_SCR_X = 1023 )THEN
					FF_ACT_X <= '0';
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_ACT_Y <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( FF_MON_Y = (2 + 47 - 1) )THEN
					FF_ACT_Y <= '1';
				ELSIF( FF_SCR_Y = 192 )THEN
					FF_ACT_Y <= '0';
				END IF;
			END IF;
		END IF;
	END PROCESS;

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_INTR_ACT_Y <= '0';
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				IF( FF_MON_Y = (2 + 47 - 1) )THEN
					FF_INTR_ACT_Y <= '1';
				ELSIF( FF_MON_Y = 255 )THEN
					FF_INTR_ACT_Y <= '0';
				END IF;
			END IF;
		END IF;
	END PROCESS;

END RTL;