-------------------------------------------------------------------------------
--  th9958_yjk.vhd
--  YJK to RGB converter for TH9958
--
--  Copyright (C) 2008 Takayuki Hara
--  All rights reserved.
-------------------------------------------------------------------------------
--
--  Redistribution and use of this software or any derivative works,
--  are permitted provided that the following conditions are met:
--
--  1. Redistributions of source code must retain the above copyright
--     notice, this list of conditions and the following disclaimer.
--  2. Redistributions in binary form must reproduce the above
--     copyright notice, this list of conditions and the following
--     disclaimer in the documentation and/or other materials
--     provided with the distribution.
--  3. Redistributions may not be sold, nor may they be used in a 
--     commercial product or activity without specific prior written
--     permission.
--
--  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
--  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
--  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
--  COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
--  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
--  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
--  LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
--  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
--  LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
--  ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
--  POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------

LIBRARY IEEE;
	USE IEEE.STD_LOGIC_1164.ALL;
	USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY TH9958_YJK IS
	PORT(
		CLK					: IN	STD_LOGIC;
		RESET_N				: IN	STD_LOGIC;
		ENABLE				: IN	STD_LOGIC;
		-- INPUT SIGNAL
		Y					: IN	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
		J					: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		K					: IN	STD_LOGIC_VECTOR(  5 DOWNTO 0 );
		-- OUTPUT SIGNAL
		R					: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
		G					: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 );
		B					: OUT	STD_LOGIC_VECTOR(  4 DOWNTO 0 )
	);
END TH9958_YJK;

ARCHITECTURE RTL OF TH9958_YJK IS
	SIGNAL FF_R				: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL FF_G				: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL FF_B				: STD_LOGIC_VECTOR(  4 DOWNTO 0 );

	SIGNAL W_Y4				: STD_LOGIC_VECTOR(  6 DOWNTO 0 );
	SIGNAL W_Y5				: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL W_J2				: STD_LOGIC_VECTOR(  6 DOWNTO 0 );
	SIGNAL W_J2K			: STD_LOGIC_VECTOR(  7 DOWNTO 0 );
	SIGNAL W_B4				: STD_LOGIC_VECTOR(  8 DOWNTO 0 );
	SIGNAL W_R				: STD_LOGIC_VECTOR(  6 DOWNTO 0 );
	SIGNAL W_G				: STD_LOGIC_VECTOR(  6 DOWNTO 0 );
	SIGNAL W_B				: STD_LOGIC_VECTOR(  6 DOWNTO 0 );
	SIGNAL W_R_LIM			: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL W_G_LIM			: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
	SIGNAL W_B_LIM			: STD_LOGIC_VECTOR(  4 DOWNTO 0 );
BEGIN

	R		<= FF_R;
	G		<= FF_G;
	B		<= FF_B;

	W_Y4	<= Y & "00";
	W_Y5	<= ('0' & W_Y4) + ("000" & Y);
	W_J2	<= J & '0';
	W_J2K	<= (W_J2(6) & W_J2) + (K(5) & K(5) & K);
	W_B4	<= (W_Y5(7) & W_Y5) + (W_J2K(7) & W_J2K);
	W_B		<= W_B4( 8 DOWNTO 2 );
	W_R		<= ("00" & Y) + (J(5) & J);
	W_G		<= ("00" & Y) + (K(5) & K);

	W_R_LIM	<= (OTHERS => '0') WHEN( W_R(6) = '1' )ELSE
			   (OTHERS => '1') WHEN( W_R(5) = '1' )ELSE
			   W_R( 4 DOWNTO 0 );
	W_G_LIM	<= (OTHERS => '0') WHEN( W_G(6) = '1' )ELSE
			   (OTHERS => '1') WHEN( W_G(5) = '1' )ELSE
			   W_G( 4 DOWNTO 0 );
	W_B_LIM	<= (OTHERS => '0') WHEN( W_B(6) = '1' )ELSE
			   (OTHERS => '1') WHEN( W_B(5) = '1' )ELSE
			   W_B( 4 DOWNTO 0 );

	PROCESS( RESET_N, CLK )
	BEGIN
		IF( RESET_N = '0' )THEN
			FF_R <= (OTHERS => '0');
			FF_G <= (OTHERS => '0');
			FF_B <= (OTHERS => '0');
		ELSIF( CLK'EVENT AND CLK = '1' )THEN
			IF( ENABLE = '1' )THEN
				FF_R <= W_R_LIM;
				FF_G <= W_G_LIM;
				FF_B <= W_B_LIM;
			END IF;
		END IF;
	END PROCESS;
END RTL;